Single-transistor electrically-alterable switch employing fowler nordheim tunneling for program and erase

Claim 2

A one-transistor, electrically-alterable switch in combination with a pass transistor, including: a first MOS transistor having a drain, a gate, and a source; a pass transistor having a drain, a source and a floating gate, said floating gate capacitively coupled to the source of said first MOS transistor through a tunneling dielectric, said drain and source of said pass transistor connected to user-programmable circuit paths in a user-programmable circuit; an erase electrode capacitively coupled to said floating gate through a coupling dielectric; and wherein said user-programmable circuit paths provide one of the functions of defining the function of circuit elements and of defining circuit paths within said user-programmable circuit.

Claim 3

A one-transistor, electrically-alterable switch in combination with a pass transistor formed on a semiconductor substrate, including: a pair of spaced-apart high-voltage switch transistor source and drain regions disposed in the semiconductor substrate and forming a switch transistor channel region therein; a switch transistor gate formed from a first portion of a polysilicon layer, said switch transistor gate overlying said switch channel region and separated from said switch channel region by a gate oxide; an erase electrode formed as a high-voltage diffused region in said substrate; a floating gate comprising a second portion of said polysilicon layer separated from an upper surface of said semiconductor substrate by a gate oxide, said floating gate partially overlying said switch transistor source region, a portion of said floating gate overlying said switch transistor source region and separated therefrom by a tunneling dielectric having a first area, said floating gate also overlying said erase electrode and separated therefrom by a coupling dielectric having a second area larger than said first area; a pair of spaced-apart pass transistor source and drain regions disposed in the semiconductor substrate and forming a pass transistor channel region therein, said spaced-apart pass transistor source and drain regions connected to user-programmable circuit paths in a user-programmable circuit; a pass transistor gate formed from said first polysilicon layer, said pass transistor gate overlying said pass channel region and separated from said pass channel region by a gate oxide, said pass transistor gate electrically connected to said floating gate; and wherein said user-programmable circuit paths provide one of the functions of defining the function of circuit elements and of defining circuit paths within said user-programmable circuit.

Claim 4

A one-transistor, electrically-alterable switch in combination with a pass transistor formed on a semiconductor substrate, including: a pair of spaced-apart high-voltage switch transistor source and drain regions disposed in the semiconductor substrate and forming a switch transistor channel region therein; a switch transistor gate formed from a first portion of a polysilicon layer, said switch transistor gate overlying said switch channel region and separated from said switch channel region by a gate oxide; an erase electrode formed as a high-voltage diffused region in said substrate; a floating gate comprising a second portion of said polysilicon layer separated from an upper surface of said semiconductor substrate by a gate oxide, said floating gate partially overlying said switch transistor source region, a portion of said floating gate overlying said switch transistor source region and separated therefrom by a tunneling dielectric having a first area, said floating gate also overlying said erase electrode and separated therefrom by a coupling dielectric having a second area larger than said first area; a pair of spaced-apart pass transistor source and drain regions disposed in the semiconductor substrate and forming a pass transistor channel region therein, said spaced-apart pass transistor source and drain regions connected to user-programmable circuit paths in a user-programmable circuit; a pass transistor gate formed from said first polysilicon layer, said pass transistor gate overlying said pass channel region and separated from said pass channel region by a gate oxide, said pass transistor gate electrically connected to said floating gate; and wherein said user-programmable circuit paths provide one of the functions of defining the function of circuit elements and of defining circuit paths within said user-programmable circuit.

Claim 5

An array of rows and columns of one-transistor, electrically-alterable switches including: a row line associated with each row of said array; a column line associated with each column of said array; a plurality of one-transistor, electrically-alterable switches, each of said switches including a first MOS transistor having a drain connected to the one of said column lines associated with its column, a gate connected to the one of said row lines associated with its row, a source, and a floating gate capacitively coupled to said source by a tunneling capacitor; a plurality of pass transistors, each pass transistor associated with one of said one-transistor, electrically-alterable switches and having a drain, a source and a gate, said gate electrically connected to the floating gate of the one of said one-transistor, electrically-alterable switches with which it is associated; a common erase electrode capacitively coupled to said floating gates of each of said pass transistors by a coupling capacitor; and programming circuitry, said programming circuitry connected to each said row line, each said column line, and said common erase electrode line for selectively driving each said row line to ground or to a programming voltage, for selectively driving each said column line to ground or to said programming voltage, and for selectively driving said common erase electrode to ground or to said programming voltage, to program and erase said electrically-alterable switches in said array.

Claim 6

An array of rows and columns of one-transistor, electrically-alterable switches including: a row line associated with each row of said array; a column line associated with each column of said array; a plurality of one-transistor, electrically-alterable switches, each of said switches including a first MOS transistor having a drain connected to the one of said column lines associated with its column, a gate connected to the one of said row lines associated with its row, a source, and a floating gate capacitively coupled to said source by a tunneling capacitor; a plurality of pass transistors, each pass transistor associated with one of said one-transistor, electrically-alterable switches and having a drain, a source and a gate, said gate electrically connected to the floating gate of the one of said one-transistor, electrically-alterable switches with which it is associated; a common erase electrode capacitively coupled to said floating gates of each of said pass transistors by a coupling capacitor; and programming circuitry, said programming circuitry connected to each said row line, each said column line, and said common erase electrode line for selectively driving each said row line to ground or to a programming voltage, for selectively driving each said column line to ground or to said programming voltage, and for selectively driving said common erase electrode to ground or to said programming voltage, to program and erase said electrically-alterable switches in said array.