Sealed charge storage structure

Claim 2

A sealed memory cell in a nonvolatile memory chip, the chip containing a plurality of memory cells, at least one of said memory cells being sealed from exposure to radian energy, the sealed memory cell comprising, a chip substrate, a source, drain and control gate defined within the chip substrate in a memory cell area and a floating gate disposed above the substrate in said memory cell area, said floating gate extending over and capacitively coupling to said control gate in a coupling area of said memory cell area, a radiant energy shielding cover in contact with said substrate in a ring completely enclosing said memory cell area, said memory cell area being totally sealed over and around all sides of said memory cell area from radiant energy by said cover, means defined within said chip substrate for electrically connecting said source, drain and control gate with corresponding connection terminals outside of said memory cell area, wherein said connecting means includes an electrically conductive channel within said substrate extending from said control gate in said coupling area, under said shielding cover, to a corresponding gate connection terminal outside of said memory cell area.

Claim 3

The sealed memory cell of claim 1 wherein said connecting means further comprises, a second electrically conductive channel within said substrate extending from said drain in said memory cell area, under said shielding cover, to a corresponding drain connection terminal outside of said memory cell area, a conductive line electrically contacting said source and said cover, said cover being electrically conductive.

Claim 4

A sealed memory cell in a nonvolatile chip, the chip containing a plurality of memory cells at least one memory cell being sealed from exposure to radiant energy, the sealed memory cell comprising, a chip substrate, a source, drain and control gate defined within the chip substrate in a memory cell area and a floating gate disposed above the substrate in a memory cell area, said floating gate extending over and capacitively coupled to said control gate in a coupling area of said memory cell area. a radiant energy shielding cover in contact with said substrate in a ring completely enclosing said memory cell area, said memory cell area being totally sealed from radiant energy over and around all sides of said memory cell area by said cover, and means defined within said chip substrate for electrically connecting said source, drain and control gate with corresponding connection terminals outside of said memory cell area, said connecting means including an electrically conductive channel within said substrate extending from said control gate in said coupling area, under said shielding cover, to a corresponding gate connection terminal outside of said memory cell area, wherein said control gate, conductive channel and gate connection terminal are collectively formed by a structure which is an N-well, said N-well extending in said coupling area under said floating gate.

Claim 5

A sealed memory cell in a nonvolatile chip, the chip containing a plurality of memory cells at least one memory cell being sealed from exposure to radiant energy, the sealed memory cell comprising, a chip substrate, a source, drain and control gate defined within the chip substrate in a memory cell area and a floating gate disposed above the substrate in a memory cell area, said floating gate extending over and capacitively coupled to said control gate in a coupling area of said memory cell area. a radiant energy shielding cover in contact with said substrate in a ring completely enclosing said memory cell area, said memory cell area being totally sealed from radiant energy over and around all sides of said memory cell area by said cover, and means defined within said chip substrate for electrically connecting said source, drain and control gate with corresponding connection terminals outside of said memory cell area, said connecting means including an electrically conductive channel within said substrate extending from said control gate in said coupling area, under said shielding cover, to a corresponding gate connection terminal outside of said memory cell area, wherein said control gate, conductive channel and gate connection terminal are collectively formed by a structure which is an N-well, said N-well extending in said coupling area under said floating gate.

Claim 6

The sealed memory cell of claim 1 wherein said floating gate extension above said capacitive coupling area has a polygonal shape.

Claim 7

The sealed memory cell of claim 1 wherein said floating gate extension above said capacitive coupling area has a forked shape with a plurality of spaced apart fingers.

Claim 8

The sealed memory cell of claim 1 wherein said cover is composed of material selected from the group consisting of metal and polysilicon.

Claim 9

A sealed memory cell in an EPROM device, the EPROM device having a substrate with a plurality of floating gate memory cells, at least one of said memory cells being sealed from erasure by ultraviolet light, said sealed memory cell comprising, spaced apart implants in a memory cell area of the substrate, said implants defining a source and a drain, a thin gate oxide layer disposed over said substrate between said source and drain implants, a polysilicon layer defining a floating gate, said polysilicon layer disposed over said thin gate oxide layer and extending therefrom to a coupling area, an ultraviolet-shielding electrically conductive cover disposed on top of said substrate with top and sides thereof respectively spaced over and around said source, drain and floating gate, said cover contacting said substrate in a ring completely surrounding said source, drain and floating gate, whereby said memory cell is completely surrounded on top and sides by said cover, electrically conductive channels defined in said substrate extending under said sides of said cover, a first of said channels extending from said drain implant in said memory cell area to a drain connection implant outside of said memory cell area, a second of said channels extending from said coupling area in said memory cell area to a gate connection implant outside of said memory cell area, said coupling area having an oxide layer between said polysilicon layer and said second channel whereby said second channel is capacitively coupled to said floating gate, and means for electrically connecting said source implant to said conductive cover, conductive lines of said EPROM device electrically communicating with said source, drain and gate via respective conductive cover, drain connection implant and gate connection implant outside said memory cell area.

Claim 10

A sealed memory cell in an EPROM device, the EPROM device having a substrate with a plurality of floating gate memory cells, at least one of said memory cells being sealed from erasure by ultraviolet light, said sealed memory cell comprising, spaced apart implants in a memory cell area of the substrate, said implants defining a source and a drain, a thin gate oxide layer disposed over said substrate between said source and drain implants, a polysilicon layer defining a floating gate, said polysilicon layer disposed over said thin gate oxide layer and extending therefrom to a coupling area, an ultraviolet-shielding electrically conductive cover disposed on top of said substrate with top and sides thereof respectively spaced over and around said source, drain and floating gate, said cover contacting said substrate in a ring completely surrounding said source, drain and floating gate, whereby said memory cell is completely surrounded on top and sides by said cover, electrically conductive channels defined in said substrate extending under said sides of said cover, a first of said channels extending from said drain implant in said memory cell area to a drain connection implant outside of said memory cell area, a second of said channels extending from said coupling area in said memory cell area to a gate connection implant outside of said memory cell area, said coupling area having an oxide layer between said polysilicon layer and said second channel whereby said second channel is capacitively coupled to said floating gate, and means for electrically connecting said source implant to said conductive cover, conductive lines of said EPROM device electrically communicating with said source, drain and gate via respective conductive cover, drain connection implant and gate connection implant outside said memory cell area.

Claim 11

The sealed memory cell of claim 7 wherein said electrically conductive channels are selected from the group of structures consisting of N-wells, buried N+ implants and buried N+ layers.

Claim 12

The sealed memory cell of claim 7 wherein said polysilicon layer over said coupling area has a polygonal shape.

Claim 13

The sealed memory cell of claim 7 wherein said polysilicon layer over said coupling area has a forked shape with a plurality of spaced apart fingers disposed over said second channel.

Claim 14

The sealed memory cell of claim 7 wherein said cover is composed of material selected from the group consisting of metal and polysilicon.

Claim 15

The sealed memory cell of claim 7 wherein said connecting means comprises a conductive layer disposed over and contacting said source implant, said conductive layer also contacting a side of said conductive cover.

Claim 16

The sealed memory cell of claim 7 wherein said source and drain are defined by arsenic N+ implants.

Claim 17

The sealed memory cell of claim 7 wherein a ring implant is disposed in said substrate beneath said sides of said cover, said channels crossing under said ring implant in crossing regions, said ring implant being a P+ implant at least in said crossing regions.