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US5828131A
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Low temperature formation of low resistivity titanium silicide
Assignee: GlobalFoundries Inc
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Filing: 1996-01-16
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Granted: 1998-10-27
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Expires: 2016-01-16
Abstract
Abstract Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900° C., and more preferably between about 600°-700° C.
Inventors
- 👤 Cyril Cabral, Jr.
- 👤 Lawrence Alfred Clevenger
- 👤 Francois Max d'Heurle
- 👤 James Mckell Edwin Harper
- 👤 Randy William Mann
- 👤 Glen Lester Miles
- 👤 James Spiros Nakos
- 👤 Ronnen Andrew Roy
- 👤 Katherine L. Saenger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:49
CPC Classifications
C; C30; C30B; C30B1/00; C30B1/02; C30B29/00; C30B29/10; H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
61 words
A semiconductor device having a titanium silicide layer comprising: a silicon layer; and a layer of titanium silicide over said silicon layer, wherein said layer of titanium silicide comprises substantially C54 phase titanium silicide and from 1 to 20 atomic percent of a second refractory metal, and wherein said titanium silicide layer has a thickness of between 10 and 200 nm.
Claim 2
Dependent Claim
61 words
A semiconductor device having a titanium silicide layer comprising: a silicon layer; and a layer of titanium silicide over said silicon layer, wherein said layer of titanium silicide comprises substantially C54 phase titanium silicide and from 1 to 20 atomic percent of a second refractory metal, and wherein said titanium silicide layer has a thickness of between 10 and 200 nm.
Claim 3
Dependent Claim
38 words
The semiconductor device of claim 1 wherein said silicon layer is selected from the group of monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium alloy, silicon on insulator having N-type dopant and silicon on insulator having P-type dopant.
Claim 4
Dependent Claim
29 words
The semiconductor device of claim 1 wherein said second refractory metal is selected from the group of one or more of the following Ta, Nb, W, V or Cr.
Claim 5
Dependent Claim
23 words
The semiconductor device of claim 1 wherein said titanium silicide layer comprises from 1 to 15 atomic percent of said second refractory metal.
Claim 6
Dependent Claim
20 words
The semiconductor device of claim 2 wherein said second refractory metal is selected from the group of Ta and Nb.
Claim 7
Dependent Claim
27 words
The semiconductor device of claim 1, wherein said second refractory metal comprises Mo. and wherein said titanium silicide layer comprises from 1 to 5 atomic percent Mo.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-26 | 2002-04-27 | 2002-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-26 | 2006-04-27 | 2006-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-26 | 2010-04-27 | 2010-10-27 | $7700.00 | Window Closed / Lapsed |