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JPS586172A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Toshiba Corp
•
Filing: 1981-07-03
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Granted: —
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Expires: 2001-07-03
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Abstract

Abstract PURPOSE:To contrive to enhance high speed operation and reliability of a semiconductor device by a method wherein an impurity element to suppress contraction of volume of a film to be generated by thermal annealing is mixed in the metal silicide film to be used as the electrode wiring. CONSTITUTION:Field oxide films 42 are formed by the selective oxidation method using a p type Si substrate 41, and after a gate oxide film 43 is formed, the Mo silicide film 44 is formed on the whole surface. The film 44 thereof is formed by the sputtering method using an Mo silicide target mixed previously with Ti. Then patterning is performed on the film 44 to form wirings for a gate electrode and the others, the source region 45 and the drain region 46 are formed by impurity diffusion, and after the whole surface is covered with a CVD oxide film 47, contact holes are formed and Al wirings 48 are formed. As the impurity element to be mixed in the metal silicide, besides Ti, the metal of Cr, Ni, etc. are desirable. As a result, crack and peel off are not generated in the electrode wiring consisting of the Mo silicide film.

Inventors

  • 👤 Shohei Shima
  • 👤 昇平 嶋

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 15:24
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60

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