Single anneal step process for forming titanium silicide on semiconductor wafer

Claim 2

An improved process for forming a conductive layer of titanium silicide on a silicon semiconductor wafer containing silicon and silicon oxide surfaces which comprises: a) forming a titanium layer over the wafer in a vacuum deposition chamber in the substantial absence of oxygenbearing gases; b) transferring the titanium coated wafer to a sealed annealing chamber without substantially exposing the newly formed titanium layer to oxygen-bearing gases; and c) annealing the titanium-coated silicon semiconductor wafer in a nitrogen-bearing atmosphere in said sealed annealing chamber, and in the substantial absence of oxygen-bearing gases, in a single annealing step without an intervening etching step comprising: i) a first annealing temperature which will form a layer of titanium silicide over silicon surfaces of said wafer, titanium nitride over said titanium silicide, and convert all of the titanium over said silicon oxide surfaces to titanium nitride; and ii) a second annealing temperature to convert said titanium silicide into a stable phase of titanium silicide on said wafer.

Claim 3

The process of claim 1 wherein said annealing step further comprises initially heating said wafer to a first temperature ranging from about 500° up to about 695° C. for a time period ranging from about 20 seconds to about 60 seconds by raising the temperature of said wafer at a rate within a range of from about 520 /second to about 150°/second to form said titanium silicide and said titanium nitride.

Claim 4

The process of claim 2 wherein said annealing step additionally comprises further annealing of said wafer at a second temperature ranging from about 800° to about 900° C. for an additional time period ranging from about 20 to about 60 seconds to convert said titanium silicide into a stable phase.

Claim 5

The process of claim 3 including the further step of etching said wafer, after said annealing step, to remove titanium nitride from said wafer.

Claim 6

The process of claim 1 wherein said annealing step comprises annealing said wafer at a first temperature ranging from about 500° up to about 695° C. for a time period ranging from about 20 seconds to about 60 seconds by raising the temperature of said wafer at a rate within a range of from about 5°/second to about 150° C./second, and then further annealing said wafer at a second temperature ranging from about 800° to about 900° C. for an additional time period ranging from about 20 to about 60 seconds.

Claim 7

The process of claim 5 wherein said annealing temperature is raised from said first temperature range up to said second temperature range by raising the temperature of said wafer at a rate of from about 520 /second to about 150° C./second.

Claim 8

The process of claim 5 which further includes reacting all of the titanium overlying silicon oxide (SiO 2 ) regions on said wafer with nitrogen in said annealing chamber during said annealing at said first temperature to form titanium nitride whereby subsequent annealing of said wafer at said second higher temperature will not result in reaction between said silicon oxide and unreacted titanium overlying said silicon oxide.

Claim 9

The process of claim 5 wherein said nitrogenbearing atmosphere in said annealing chamber is maintained, during said first annealing step, at a pressure ranging from about 100 milliTorr to about 800 Torr while flowing one or more nitrogen-bearing gases into said chamber at a rate ranging from about 500 to about 10,000 sccm.

Claim 10

The process of claim 1 wherein said annealing step further comprises annealing said wafer at a first temperature ranging from about 600 ° up to about 675° C. for a time period ranging from about 20 seconds to about 60 seconds by raising the temperature of said wafer at a rate within a range of from about 5°/second to about 150° C./second, and then further annealing said wafer at a second temperature ranging from about 800° to about 900° C. for an additional time period ranging from the temperature of said wafer at a rate of from about 5°/second to about 150° C./second.

Claim 11

The process of claim 6 which further includes transferring said wafer from said vacuum deposition chamber to said sealed annealing chamber through a sealed central chamber maintained at a pressure ranging from about 10 -9 to about 10 -5 Torr which is interconnected to both said vacuum deposition chamber and said sealed annealing chamber to avoid substantially exposing the newly formed titanium layer to oxygen and/or oxygen-bearing gases.

Claim 12

The process of claim 6 which comprises the further steps of: a) cleaning said wafer in a cleaning chamber using a gaseous mixture which includes at least one reactive gas while maintaining an rf plasma in said cleaning chamber to remove oxides and other materials from the silicon surfaces thereon prior to said titanium deposition step; and b) transferring said cleaned wafer from said cleaning chamber to said vacuum deposition without substantially exposing said cleaned wafer to oxygen and/or one or more oxygen-bearing gases using a sealed central chamber maintained at a pressure ranging from about 10 -9 to about 10 -5 Torr which is interconnected to both said cleaning chamber and said vacuum deposition chamber.

Claim 13

The process of claim 11 wherein said cleaning step further comprises flowing into said cleaning chamber a gaseous mixture containing at least one reactive gas at a rate of from about 2 to about 500 sccm reactive gas and from about 10 to about 1000 sccm carrier gas while maintaining said plasma at a power ranging from about 20 to about 500 watts for a period of time ranging from about 1 to about 500 seconds.

Claim 14

The process of claim 6 wherein said titanium deposition step further comprises depositing a titanium layer ranging in thickness from about 100 to about 5000 Angstroms.

Claim 15

An improved process for forming titanium silicide on a silicon semiconductor wafer using a single annealing step at first and second temperature without an intervening etching step which comprises: a) providing a silicon semiconductor wafer having one or more silicon surface regions on which said titanium silicide is to be formed; b) cleaning said wafer in a sealed cleaning chamber using an rf plasma and a gaseous mixture which includes at least one reactive gas; c) transferring the cleaned wafer to a vacuum deposition chamber without substantially exposing said cleaned wafer to oxygen-bearing gases by transferring said wafer through a sealed central chamber which is interconnected to both said vacuum deposition chamber and said cleaning chamber; d) forming a titanium layer over said cleaned wafer in said vacuum deposition chamber in the substantial absence of oxygen-bearing gases; e) transferring the titanium coated wafer to an annealing chamber without substantially exposing the newly formed titanium layer to oxygen-bearing gases by transferring said wafer through a sealed central chamber which is interconnected to both said vacuum deposition chamber and said sealed annealing chamber; and f) annealing the titanium-coated silicon semiconductor wafer in a nitrogen-bearing atmosphere in said annealing chamber, and in the substantial absence of oxygen-bearing gases, by initially heating said wafer to a first temperature ranging from about 500° up to about 695° C. for a time period ranging from about 20 seconds to about 60 seconds by raising the temperature of said wafer at a rate within a range of from about 5°/second to about 150° C./second to form titanium silicide, and to form titanium nitride over said titanium silicide and over silicon oxide (SiO 2 ) surfaces on said wafer, and then, without removing the wafer from said annealing chamber, further annealing said wafer at a second temperature ranging from about 800° to about 900° C. for an additional time period ranging from about 20 to about 60 seconds to convert said titanium silicide to a stable phase.

Claim 16

An improved process for forming titanium silicide on a silicon semiconductor wafer using a single annealing step at first and second temperature without an intervening etching step which comprises: a) providing a silicon semiconductor wafer having one or more silicon surface regions on which said titanium silicide is to be formed; b) cleaning said wafer in a sealed cleaning chamber using an rf plasma and a gaseous mixture which includes at least one reactive gas; c) transferring the cleaned wafer to a vacuum deposition chamber without substantially exposing said cleaned wafer to oxygen-bearing gases by transferring said wafer through a sealed central chamber which is interconnected to both said vacuum deposition chamber and said cleaning chamber; d) forming a titanium layer over said cleaned wafer in said vacuum deposition chamber in the substantial absence of oxygen-bearing gases; e) transferring the titanium coated wafer to an annealing chamber without substantially exposing the newly formed titanium layer to oxygen-bearing gases by transferring said wafer through a sealed central chamber which is interconnected to both said vacuum deposition chamber and said sealed annealing chamber; and f) annealing the titanium-coated silicon semiconductor wafer in a nitrogen-bearing atmosphere in said annealing chamber, and in the substantial absence of oxygen-bearing gases, by initially heating said wafer to a first temperature ranging from about 500° up to about 695° C. for a time period ranging from about 20 seconds to about 60 seconds by raising the temperature of said wafer at a rate within a range of from about 5°/second to about 150° C./second to form titanium silicide, and to form titanium nitride over said titanium silicide and over silicon oxide (SiO 2 ) surfaces on said wafer, and then, without removing the wafer from said annealing chamber, further annealing said wafer at a second temperature ranging from about 800° to about 900° C. for an additional time period ranging from about 20 to about 60 seconds to convert said titanium silicide to a stable phase.

Claim 17

The process of claim 14 including the further step of etching said wafer, after said annealing step, to remove titanium nitride from said wafer.

Claim 18

The process of claim 14 wherein said first annealing temperature ranges from about 600° to about 675° C.

Claim 19

The process of claim 14 which further includes reacting all of the titanium overlying silicon oxide (SiO 2 ) regions on said wafer with nitrogen in said annealing chamber during said annealing at said first temperature to form titanium nitride whereby subsequent annealing of said wafer at said second higher temperature will not result in reaction between said silicon oxide and unreacted titanium overlying said silicon oxide.

Claim 20

An improved process for forming titanium silicide on a silicon semiconductor wafer using a single annealing step at first and second temperature without an intervening etching step which comprises: a) providing a silicon semiconductor wafer having one or more silicon surface regions on which said titanium silicide is to be formed; b) cleaning said wafer in a sealed cleaning chamber using an rf plasma and a gaseous mixture containing at least one reactive gas; c) transferring the cleaned wafer to a vacuum deposition chamber without substantially exposing said cleaned wafer to oxygen-bearing gases by transferring said wafer through a sealed central chamber which is interconnected to both said vacuum deposition chamber and said cleaning chamber; d) forming a titanium layer over said cleaned wafer in said vacuum deposition chamber in the substantial absence of oxygen-bearing gases; e) transferring the titanium coated wafer to an annealing chamber without substantially exposing the newly formed titanium layer to oxygen-bearing gases by transferring said wafer through a sealed central chamber which is interconnected to both said vacuum deposition chamber and said sealed annealing chamber; f) annealing the titanium-coated silicon semiconductor wafer in a nitrogen-bearing atmosphere in said annealing chamber, and in the substantial absence of oxygen-bearing gases, at a first temperature ranging from about 600° to about 675° C. for a period of time ranging from about 20 seconds to about 60 seconds by raising the temperature of said wafer at a rate within a range of from about 520 /second to about 150° C./second to form said titanium silicide, as well as to form titanium nitride over said titanium silicide which inhibits migration of underlying silicon to the surface, and to react substantially all of the titanium overlying silicon oxide (SiO 2 ) regions on said wafer to form titanium nitride, whereby subsequent annealing of said wafer at a higher temperature will not result in reaction between said silicon oxide and unreacted titanium overlying said silicon oxide; and g) then, without removing the wafer from said annealing chamber, raising the wafer temperature at a rate within a range of from about 5°/second to about 150° C./second to a second temperature ranging from about 800° to about 900° C. to further anneal said wafer for an additional time period ranging from about 20 to about 60 seconds to convert said titanium silicide into a stable phase.

Claim 21

An improved process for forming titanium silicide on a silicon semiconductor wafer using a single annealing step at first and second temperature without an intervening etching step which comprises: a) providing a silicon semiconductor wafer having one or more silicon surface regions on which said titanium silicide is to be formed; b) cleaning said wafer in a sealed cleaning chamber using an rf plasma and a gaseous mixture containing at least one reactive gas; c) transferring the cleaned wafer to a vacuum deposition chamber without substantially exposing said cleaned wafer to oxygen-bearing gases by transferring said wafer through a sealed central chamber which is interconnected to both said vacuum deposition chamber and said cleaning chamber; d) forming a titanium layer over said cleaned wafer in said vacuum deposition chamber in the substantial absence of oxygen-bearing gases; e) transferring the titanium coated wafer to an annealing chamber without substantially exposing the newly formed titanium layer to oxygen-bearing gases by transferring said wafer through a sealed central chamber which is interconnected to both said vacuum deposition chamber and said sealed annealing chamber; f) annealing the titanium-coated silicon semiconductor wafer in a nitrogen-bearing atmosphere in said annealing chamber, and in the substantial absence of oxygen-bearing gases, at a first temperature ranging from about 600° to about 675° C. for a period of time ranging from about 20 seconds to about 60 seconds by raising the temperature of said wafer at a rate within a range of from about 520 /second to about 150° C./second to form said titanium silicide, as well as to form titanium nitride over said titanium silicide which inhibits migration of underlying silicon to the surface, and to react substantially all of the titanium overlying silicon oxide (SiO 2 ) regions on said wafer to form titanium nitride, whereby subsequent annealing of said wafer at a higher temperature will not result in reaction between said silicon oxide and unreacted titanium overlying said silicon oxide; and g) then, without removing the wafer from said annealing chamber, raising the wafer temperature at a rate within a range of from about 5°/second to about 150° C./second to a second temperature ranging from about 800° to about 900° C. to further anneal said wafer for an additional time period ranging from about 20 to about 60 seconds to convert said titanium silicide into a stable phase.

Claim 22

The process of claim 18 including the further step of etching said wafer, after said annealing step, to remove titanium nitride from said wafer.