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US5824588A
Expired / Lapsed
US
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Double spacer salicide MOS process and device
Assignee: Nuvoton Technology Corp
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Filing: 1996-09-24
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Granted: 1998-10-20
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Expires: 2016-09-24
Abstract
Abstract A double spacer salicide MOS device structure and a process for preparing such a device. The double spacer salicide device has a LDD structure. The first sidewall spacer disposed adjacent to the gate structure of the MOS device is higher than the gate. During the salicide process, the first sidewall spacer is used to effectively isolate the gate from the source/drain. The second sidewall spacer disposed adjacent to the first sidewall spacer is used to form the LDD structure.
Inventors
- 👤 Han-Hsing Liu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:03
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0212; H10D64/00; H10D64/01; H10D64/021; H10D64/017
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
172 words
A method for fabricating salicide MOS devices on a substrate, comprising the steps of: depositing an oxide layer on said substrate; depositing a polysilicon layer on said oxide layer; depositing a stuffed layer on said polysilicon layer; etching said stuffed layer, said polysilicon layer and said oxide layer through a prescribed photomask which defines said polysilicon layer and said oxide layer as a gate structure; forming a first dielectric layer continuously on a top face and side walls of said stuffed layer and said gate structure; forming lightly doped source and drain regions in said substrate adjacent to the side walls of said gate structure; anisotropically etching said first dielectric layer to form a first spacer at the side walls of said gate structure; forming a second spacer at side walls of said first spacer; removing said stuffed layer; forming heavily doped source and drain regions in said substrate adjacent to said lightly doped source and drain regions, respectively; and forming salicide regions upon said gate structure and said heavily doped regions.
Claim 2
Independent Claim
172 words
A method for fabricating salicide MOS devices on a substrate, comprising the steps of: depositing an oxide layer on said substrate; depositing a polysilicon layer on said oxide layer; depositing a stuffed layer on said polysilicon layer; etching said stuffed layer, said polysilicon layer and said oxide layer through a prescribed photomask which defines said polysilicon layer and said oxide layer as a gate structure; forming a first dielectric layer continuously on a top face and side walls of said stuffed layer and said gate structure; forming lightly doped source and drain regions in said substrate adjacent to the side walls of said gate structure; anisotropically etching said first dielectric layer to form a first spacer at the side walls of said gate structure; forming a second spacer at side walls of said first spacer; removing said stuffed layer; forming heavily doped source and drain regions in said substrate adjacent to said lightly doped source and drain regions, respectively; and forming salicide regions upon said gate structure and said heavily doped regions.
Claim 3
Dependent Claim
26 words
A method as recited in claim 1, wherein said stuffed layer is made of silicon oxide with a thickness of between 200 Å and 600 Å.
Claim 4
Dependent Claim
22 words
A method as recited in claim 2, wherein said stuffed layer made of silicon oxide is formed by low-pressure chemical vapor deposition.
Claim 5
Dependent Claim
22 words
A method as recited in claim 2, wherein said stuffed layer made of silicon oxide is formed by plasma-enhanced chemical vapor deposition.
Claim 6
Dependent Claim
27 words
A method as recited in claim 7, wherein said first dielectric layer is made of silicon nitride with a thickness of between 100 Å and 400 Å.
Claim 7
Dependent Claim
23 words
A method as recited in claim 5, wherein said first dielectric layer made of silicon nitride is formed by low-pressure chemical vapor deposition.
Claim 8
Dependent Claim
63 words
A method as recited in claim 1, wherein said salicide structure is formed by the steps of: depositing a metal layer continuously over said gate structure and said heavily doped regions; reacting said metal layer with silicon material of said gate structure and said heavily doped regions to form silicide compound by a thermal treatment; and removing unreacted material from said metal layer.
Claim 9
Dependent Claim
15 words
A method as recited in claim 7, wherein said metal layer is made of titanium.
Claim 10
Dependent Claim
15 words
A method as recited in claim 7, wherein said metal layer is made of platinum.
Claim 11
Dependent Claim
75 words
A method as recited in claim 1, wherein: said stuffed layer is deposited with a pre-determined thickness; said first spacer is made higher than said polysilicon layer of said gate structure by the predetermined thickness of said stuffed layer; said second spacer is formed of a different material than said first spacer; and the salicide regions on said gate structure are isolated from the salicide regions on said heavily doped regions by the first spacer.
Claim 12
Dependent Claim
105 words
A method as recited in claim 10, wherein: said stuffed layer is made of silicon oxide with a thickness of between 200 Å and 600 Å; said first dielectric layer is made of silicon nitride with a thickness of between 100 Å and 400 Å; and said second spacer is formed by the steps of: forming a second dielectric layer made of silicon oxide with a thickness of between 1000 Å and 3000 Å continuously over said stuffed layer, said first spacer and said substrate; and anisotropically etching said second dielectric layer to form said second spacer at the side walls of said first spacer.
Claim 13
Dependent Claim
35 words
A method as recited in claim 10, wherein said second spacer and said stuffed layer are formed by the same material and said stuffed layer is removed by the step of forming said second spacer.
Claim 14
Dependent Claim
53 words
A method as recited in claim 10, wherein said second spacer is formed by the steps of: forming a second dielectric layer continuously over said stuffed layer, said first spacer and said substrate; and anisotropically etching said second dielectric layer to form said second spacer at the side walls of said first spacer.
Claim 15
Dependent Claim
27 words
A method as recited in claim 13, wherein said second dielectric layer is made of silicon oxide with a thickness of between 1000 Å and 3000 Å.
References Cited (Backward Citations)
JPS607126A
Cited
JPH02135A
Cited
US5424234A
Cited
EP0575099A1
Cited
US5330925A
Cited
US5352631A
Cited
US5496751A
Cited
US5468665A
Cited
US5518945A
Cited
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| 3.5 Years (Year 4) | 2001-10-19 | 2002-04-20 | 2002-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-19 | 2006-04-20 | 2006-10-20 | $3760.00 | Window Closed / Lapsed |
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