US5468665A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for making a semiconductor MOS transistor employing a temporary spacer
Assignee: MagnaChip Semiconductor Ltd
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Filing: 1995-01-23
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Granted: 1995-11-21
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Expires: 2015-01-23
Abstract
Abstract In the method of present invention, an LDD MOSFET is formed without using a side wall spacer as an ion implantation inhibiting layer. The process includes the steps of: forming a first insulating layer, a conductive layer and an auxiliary layer upon a semiconductor substrate, removing relevant portions of the auxiliary layer to form an auxiliary layer pattern such as a gate pattern on the conductive layer; depositing a temporary layer on the auxiliary layer pattern and on the exposed conductive layer, and etching it back to form a temporary layer spacer on the side wall of the auxiliary layer pattern; removing relevant portions of the conductive layer utilizing the auxiliary layer pattern and the temporary layer spacer as a mask, and forming a high concentration first dopant buried layer within the semiconductor substrate; and removing the temporary layer spacer, forming a gate electrode by etching the conductive layer utilizing the auxiliary layer pattern as a mask, and forming a low concentration second dopant buried layer within the semiconductor substrate. Applications to form CMOS devices are also disclosed.
Inventors
- 👤 Chang-Jae Lee
- 👤 Hyunsang Hwang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:32
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0184; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
126 words
A process for forming a MOSFET comprising the steps of: (a) forming a first insulating layer, a conductive layer and an auxiliary layer upon a semiconductor substrate; (b) etching portions of the auxiliary layer to form an auxiliary layer pattern; (c) forming a temporary layer side wall spacer at the sides of the auxiliary layer pattern; (d) etching portions of the conductive layer utilizing the auxiliary layer pattern and the temporary layer spacer as a mask, and forming a high concentration first dopant buried layer within the semiconductor substrate; and (e) removing the temporary layer spacer, forming a gate electrode by etching the conductive layer utilizing the auxiliary layer pattern as a mask, and forming a low concentration second dopant buried layer within the semiconductor substrate.
Claim 2
Dependent Claim
126 words
A process for forming a MOSFET comprising the steps of: (a) forming a first insulating layer, a conductive layer and an auxiliary layer upon a semiconductor substrate; (b) etching portions of the auxiliary layer to form an auxiliary layer pattern; (c) forming a temporary layer side wall spacer at the sides of the auxiliary layer pattern; (d) etching portions of the conductive layer utilizing the auxiliary layer pattern and the temporary layer spacer as a mask, and forming a high concentration first dopant buried layer within the semiconductor substrate; and (e) removing the temporary layer spacer, forming a gate electrode by etching the conductive layer utilizing the auxiliary layer pattern as a mask, and forming a low concentration second dopant buried layer within the semiconductor substrate.
Claim 3
Dependent Claim
27 words
The process as claimed in claim 1, wherein, at step (a), the first insulating layer is formed by applying a thermal oxidation process to form silicon oxide.
Claim 4
Dependent Claim
16 words
The process as claimed in claim 1, wherein, at step (a), the conductive layer comprises polysilicon.
Claim 5
Dependent Claim
34 words
The process as claimed in claim 1, wherein, at step (a), the conductive layer is formed by depositing an in-situ doped polysilicon to a thickness of about 2000 Å by applying an LPCVD process.
Claim 6
Dependent Claim
24 words
The process as claimed in claim 1, wherein, at step (a), the auxiliary layer is formed by depositing silicon oxide applying a CVD method.
Claim 7
Dependent Claim
19 words
The process as claimed in claim 1, wherein, at step (c), the temporary side wall spacer comprises silicon nitride.
Claim 8
Dependent Claim
61 words
The process as claimed in claim 6, wherein the temporary layer side wall spacer is formed by depositing silicon nitride to a thickness of about 1500 Å by applying an LPCVD method, and by carrying out an anisotropic etching on the silicon nitride using a CHF 3 /CF 4 gas plasma and utilizing the conductive layer as an etch stop layer.
Claim 9
Dependent Claim
52 words
The process as claimed in claim 1, wherein the conductive layer is etched by applying a dry etching process using the auxiliary layer pattern and the temporary layer spacer as an etch inhibiting layer, and using the first insulating layer as an etch stop layer, and using an HBr/Cl 2 gas plasma.
Claim 10
Dependent Claim
41 words
The process as claimed in claim 1, wherein the first dopant buried layer is formed with a first ion implantation method using As ions at a concentration of about 5.0×10 15 ions/cm 2 and with an energy of about 40 KeV.
Claim 11
Dependent Claim
41 words
The process as claimed in claim 1, wherein the second dopant buried layer is formed with a second ion implantation method using phosphorus ions at a concentration of about 2.0×10 13 ions/cm 2 and with an energy of about 30 KeV.
Claim 12
Dependent Claim
35 words
The process as claimed in claim 1, wherein the temporary layer spacer is removed with a wet etching method by dipping into an H 3 PO 4 solution at a temperature of about 180° C.
Claim 13
Dependent Claim
40 words
The process as claimed in claim 1, wherein, at step (a), conductive layer is formed as a first conductive layer comprising a conductive material, and the auxiliary layer is formed as a second conductive layer comprising a second conductive material.
Claim 14
Dependent Claim
21 words
The process as claimed in claim 12, wherein the first conductive layer comprises polysilicon, and the second conductive layer comprises silicide.
Claim 15
Dependent Claim
51 words
The process as claimed in claim 12, wherein the first conductive layer is formed by depositing an in-situ doped polysilicon to a thickness of about 2000 Å using an LPCVD method, and the second conductive layer is formed by depositing a CVD W silicide to a thickness of about 1500 Å.
Claim 16
Dependent Claim
62 words
The process as claimed in claim 12, wherein the temporary layer side wall spacer is formed by depositing silicon nitride to a thickness of about 1500 Å based on an LPCVD method, and carrying out an anisotropic etching on the silicon nitride layer using a CHF 3 /CF 4 gas plasma and utilizing the first conductive layer as an etch stop layer.
Claim 17
Dependent Claim
31 words
The process as claimed in claim 1, wherein, after step (e), the first and second dopant buried layers are heat-treated at a temperature of about 870° C. for about 40 minutes.
Claim 18
Dependent Claim
17 words
The process as claimed in claim 1, wherein the semiconductor substrate comprises a p type silicon substrate.
Claim 19
Dependent Claim
38 words
The process as claimed in claim 1, wherein the first dopant buried region is formed using BF 2 or B ions at a concentration of about 5.0×10 15 ions/cm 2 and with an energy of about 40 KeV.
Claim 20
Dependent Claim
38 words
The process as claimed in claim 1, wherein the second dopant buried region is formed using BF 2 or B ions at a concentration of about 2.0×10 13 ions/cm 2 and with an energy of about 30 KeV.
Claim 21
Dependent Claim
224 words
A process for formation of a CMOS semiconductor device, comprising the steps of: (a) forming a first insulating layer, a conductive layer and an auxiliary layer upon a semiconductor substrate; etching portions of the auxiliary layer to form an auxiliary layer pattern; forming a temporary layer side wall spacer at the sides of the auxiliary layer pattern; (b) defining an NMOS region, and etching the conductive layer using the temporary side wall spacer and the auxiliary layer pattern of the NMOS region as a mask; forming an n type heavily doped region using the etched conductive layer as a mask; removing the temporary side wall spacer, and etching the conductive layer using the auxiliary layer pattern as a mask to form an NMOS gate electrode; forming an n type lightly doped region using the NMOS gate electrode as a mask; (c) defining a PMOS region, and etching the conductive layer using the temporary side wall spacer and the auxiliary layer pattern of the PMOS region as a mask; forming a p type heavily doped region using the etched conductive layer as a mask; removing the temporary side wall spacer, and etching the conductive layer using the auxiliary layer pattern as a mask to form a PMOS gate electrode; and forming a p type lightly doped region using the PMOS gate electrode as a mask.
Claim 22
Dependent Claim
224 words
A process for formation of a CMOS semiconductor device, comprising the steps of: (a) forming a first insulating layer, a conductive layer and an auxiliary layer upon a semiconductor substrate; etching portions of the auxiliary layer to form an auxiliary layer pattern; forming a temporary layer side wall spacer at the sides of the auxiliary layer pattern; (b) defining an NMOS region, and etching the conductive layer using the temporary side wall spacer and the auxiliary layer pattern of the NMOS region as a mask; forming an n type heavily doped region using the etched conductive layer as a mask; removing the temporary side wall spacer, and etching the conductive layer using the auxiliary layer pattern as a mask to form an NMOS gate electrode; forming an n type lightly doped region using the NMOS gate electrode as a mask; (c) defining a PMOS region, and etching the conductive layer using the temporary side wall spacer and the auxiliary layer pattern of the PMOS region as a mask; forming a p type heavily doped region using the etched conductive layer as a mask; removing the temporary side wall spacer, and etching the conductive layer using the auxiliary layer pattern as a mask to form a PMOS gate electrode; and forming a p type lightly doped region using the PMOS gate electrode as a mask.
Claim 23
Dependent Claim
30 words
The process as claimed in claim 20, wherein the temporary layer side wall spacer comprises silicon nitride having an etch selectivity relative to the conductive layer and the auxiliary layer.
Claim 24
Dependent Claim
36 words
The process as claimed in claim 20, wherein, at step (b), after the n type heavily doped region is formed, it is heat-treated at a temperature of about 900° C. under an O 2 gas atmosphere.
Claim 25
Dependent Claim
51 words
The process as claimed in claim 20, wherein, after carrying out step (a), a first oxide layer is formed, and an NMOS region is opened during the NMOS process; and after carrying out step (b), a second oxide layer is formed, and a PMOS region is opened during the PMOS process.
Claim 26
Dependent Claim
19 words
The process as claimed in claim 20, wherein the semiconductor substrate is provided with p wells and n wells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-20 | 1999-05-22 | 1999-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-20 | 2003-05-22 | 2003-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-20 | 2007-05-22 | 2007-11-21 | $7700.00 | Window Closed / Lapsed |