US5061647A
Expired / Lapsed
US
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ITLDD transistor having variable work function and method for fabricating the same
Assignee: Motorola Solutions Inc
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Filing: 1990-10-12
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Granted: 1991-10-29
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Expires: 2010-10-12
Abstract
Abstract A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (Φ) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer. A work function adjusting layer (46) overlies and is in intimate contact with at least the lateral extensions of the IT-gate. The presence of the work function adjusting layer changes the electrical characteristics of the extensions relative to the central section of the IT-gate. Heavily doped source and drain regions (52, 53) of the second conductivity type are formed in the substrate adjacent to the first and second lightly doped regions and aligned to the edge of the gate extensions.
Inventors
- 👤 Scott S. Roth
- 👤 Carlos A. Mazure
- 👤 Kent J. Cooper
- 👤 Wayne J. Ray
- 👤 Michael P. Woo
- 👤 Jung-Hui Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 11:38
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D30/605; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01324; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D64/60; H10D64/66; H10D64/671
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
132 words
A method for forming a semiconductor device comprising: providing a semiconductor substrate having a gate dielectric thereon; forming a conductive layer overlying the gate dielectric having a relatively thick central region and a relatively thin peripheral region wherein the thick central region is protected by a cap differentially etchable with respect to the conductive layer; conformably depositing a layer of work function adjusting material to overlie the conductive layer and the cap; anisotropically etching the work function adjust material to form a Φ adjust layer overlying a portion of the peripheral region adjacent to the central region; and anisotropically etching the peripheral region to form an IT-gate having a relatively thick central portion and a thin lateral extension wherein a portion of the sidewall layer overlies the lateral extension of the IT-gate.
Claim 2
Independent Claim
132 words
A method for forming a semiconductor device comprising: providing a semiconductor substrate having a gate dielectric thereon; forming a conductive layer overlying the gate dielectric having a relatively thick central region and a relatively thin peripheral region wherein the thick central region is protected by a cap differentially etchable with respect to the conductive layer; conformably depositing a layer of work function adjusting material to overlie the conductive layer and the cap; anisotropically etching the work function adjust material to form a Φ adjust layer overlying a portion of the peripheral region adjacent to the central region; and anisotropically etching the peripheral region to form an IT-gate having a relatively thick central portion and a thin lateral extension wherein a portion of the sidewall layer overlies the lateral extension of the IT-gate.
Claim 3
Dependent Claim
33 words
The method of claim 1 wherein the first conductive layer is polycrystalline silicon and the Φ adjust layer is a refractory metal selected from the group consisting of titanium, molybdenum, tungsten and cobalt.
Claim 4
Dependent Claim
46 words
The method of claim 1 further comprising: conformably depositing a spacer forming layer to overlie the work function adjusting layer; and anisotropically etching the spacer forming layer to form a sidewall spacer on the central region of the conductive layer overlying the work function adjust material.
Claim 5
Dependent Claim
56 words
The method of claim 1 further comprising: forming lightly doped regions in the substrate using the cap and the relatively thick central region of the conductive layer as a doping mask; and forming heavily doped regions in the substrate adjacent to the lightly doped regions using the peripheral portion of the IT-gate as a doping mask
Claim 6
Independent Claim
191 words
A method for forming an IT-gate in an ITLDD semiconductor device comprising: providing a semiconductor substrate having a gate dielectric layer thereon; depositing a first conductive layer to overlie the gate dielectric layer; forming a composite hardmask comprising a second conductive layer overlying an insulating layer on a central portion of the first conductive layer; simultaneously etching the second conductive layer and the first conductive layer to remove the second conductive layer and to form a relatively thick central portion underlying the insulating layer and a relatively thin peripheral region extending laterally from the central portion long the gate dielectric layer; depositing a layer of work function adjusting material to overlie the central portion and the peripheral region; and anisotropically etching the layer of work function adjusting material to form a sidewall spacer on the central portion and overlying a portion of the peripheral region adjacent to the central portion; and anisotropically etching the peripheral region using the sidewall spacer as an etch mask to form an IT-gate having gate lateral extensions projecting from the central portion along the gate oxide and having a portion of work function adjusting material thereon.
Claim 7
Independent Claim
191 words
A method for forming an IT-gate in an ITLDD semiconductor device comprising: providing a semiconductor substrate having a gate dielectric layer thereon; depositing a first conductive layer to overlie the gate dielectric layer; forming a composite hardmask comprising a second conductive layer overlying an insulating layer on a central portion of the first conductive layer; simultaneously etching the second conductive layer and the first conductive layer to remove the second conductive layer and to form a relatively thick central portion underlying the insulating layer and a relatively thin peripheral region extending laterally from the central portion long the gate dielectric layer; depositing a layer of work function adjusting material to overlie the central portion and the peripheral region; and anisotropically etching the layer of work function adjusting material to form a sidewall spacer on the central portion and overlying a portion of the peripheral region adjacent to the central portion; and anisotropically etching the peripheral region using the sidewall spacer as an etch mask to form an IT-gate having gate lateral extensions projecting from the central portion along the gate oxide and having a portion of work function adjusting material thereon.
Claim 8
Dependent Claim
41 words
The method of claim 5 wherein the partial etch of the first conductive layer is performed in an etching apparatus equipped with an end-point detection system which terminates the etch when the second conductive layer is completely removed from insulating layer.
Claim 9
Dependent Claim
110 words
The method of claim 5 wherein forming a composite hardmask comprises the steps of: depositing a buffer layer to overlie the first conductive layer; depositing a second conductive layer to overlie the buffer layer; forming a resist mask pattern on the buffer layer; anisotropically etching the first conductive layer to form a portion thereof underlying the resist pattern having a width L1; isotropically etching the portion underlying the resist pattern from its periphery to reduce the width of the portion to L2, wherein L2 is less than L1; removing the resist pattern; and anisotropically etching the buffer layer using the portion of the second conductive layer as an etch mask.
Claim 10
Dependent Claim
34 words
The method of claim 5 wherein the first conductive layer is polycrystalline silicon and the work function adjusting material is a refractory metal selected from the group consisting of titanium, molybdenum, tungsten and cobalt.
Claim 11
Dependent Claim
42 words
The method of claim 5 further comprising: depositing a layer of spacer forming material to overlie the work function adjusting layer; and anisotropically etching the spacer forming material to form a portion of the sidewall spacer overlying the work function adjusting layer.
Claim 12
Dependent Claim
91 words
The method of claim 5 further comprising: after partially etching the first conductive layer, implanting conductivity determining dopant atoms into the substrate through the peripheral region to form lightly doped regions in the substrate aligned to the edge of the central portion wherein the lightly doped regions are separated by a channel region underlying the central portion; and after forming the IT-gate, implanting conductivity determining dopant atoms into the substrate to form a heavily doped regions adjacent to the lightly doped regions and aligned to the edge of the lateral extensions.
Claim 13
Dependent Claim
24 words
The method of claim 5 wherein the first conductive layer is N-doped polycrystalline silicon and the work function adjusting layer is P-doped polycrystalline silicon.
Claim 14
Independent Claim
239 words
A method for fabricating an ITLDD semiconductor device comprising: providing a semiconductor substrate having a gate dielectric layer, a first conductive layer, a buffer layer and a second conductive layer formed sequentially thereon; forming a resist mask on the second conductive layer; anisotropically etching away unmasked portions of the second conductive layer; further etching the masked portion of the second conductive laterally from its periphery to form a narrow segment underlying the resist mask; removing the resist mask; etching the buffer layer using the narrow segment as an etch mask leaving a remaining portion of the buffer layer underlying the narrow region; anisotropically etching exposed portions of the first conductive layer partially while simultaneously etching away the narrow segment overlying the remaining portion of the buffer layer to form a conductive body having a relatively thick central portion underlying the remaining portion of the buffer layer and a relatively thin peripheral portion; conformably depositing a work function adjusting material to overlie the conductive body and the remaining portion of the buffer layer; conformably depositing a spacer forming material to overlie the work function adjusting material; anisotropically etching the spacer forming material to form a sidewall spacer on the relatively thick portion of the conductive body; anisotropically etching the work function adjusting material using the sidewall spacer as an etch mask; and anisotropically etching the first conductive layer using the sidewall spacer as an etch mask to form an IT-gate.
Claim 15
Independent Claim
239 words
A method for fabricating an ITLDD semiconductor device comprising: providing a semiconductor substrate having a gate dielectric layer, a first conductive layer, a buffer layer and a second conductive layer formed sequentially thereon; forming a resist mask on the second conductive layer; anisotropically etching away unmasked portions of the second conductive layer; further etching the masked portion of the second conductive laterally from its periphery to form a narrow segment underlying the resist mask; removing the resist mask; etching the buffer layer using the narrow segment as an etch mask leaving a remaining portion of the buffer layer underlying the narrow region; anisotropically etching exposed portions of the first conductive layer partially while simultaneously etching away the narrow segment overlying the remaining portion of the buffer layer to form a conductive body having a relatively thick central portion underlying the remaining portion of the buffer layer and a relatively thin peripheral portion; conformably depositing a work function adjusting material to overlie the conductive body and the remaining portion of the buffer layer; conformably depositing a spacer forming material to overlie the work function adjusting material; anisotropically etching the spacer forming material to form a sidewall spacer on the relatively thick portion of the conductive body; anisotropically etching the work function adjusting material using the sidewall spacer as an etch mask; and anisotropically etching the first conductive layer using the sidewall spacer as an etch mask to form an IT-gate.
Claim 16
Dependent Claim
99 words
The method of claim 12 further comprising: after partially etching the first conductive layer, implanting conductivity determining dopant atoms into the substrate through the peripheral portion of the conductive body to form lightly doped regions in the substrate aligned to the edge of the central portion of the conductive body wherein the lightly doped regions are separated by a channel region underlying the central portion; and after forming the IT-gate, implanting conductivity determining dopant atoms into the substrate to form a heavily doped regions adjacent to the lightly doped regions and aligned to the edge of the gate extensions.
Claim 17
Dependent Claim
34 words
The method of claim 12 wherein the first conductive layer is polycrystalline silicon and the work function adjusting material is a refractory metal selected from the group consisting of titanium, molybdenum, tungsten and cobalt.
Claim 18
Dependent Claim
41 words
The method of claim 12 wherein the partial etch of the first conductive layer is performed in an etching apparatus equipped with an end-point detection system which terminates the etch when the second conductive layer is completely removed from insulating layer.
Claim 19
Dependent Claim
24 words
The method of claim 12 wherein the first conductive layer is N-doped polycrystalline silicon and the work function adjusting layer is P-doped polycrystalline silicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-28 | 1995-04-29 | 1995-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-28 | 1999-04-29 | 1999-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-28 | 2003-04-29 | 2003-10-29 | $7700.00 | Window Closed / Lapsed |