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US4774201A
Expired / Lapsed
US
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Tungsten-silicide reoxidation technique using a CVD oxide cap
Assignee: Intel Corp
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Filing: 1988-01-07
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Granted: 1988-09-27
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Expires: 2008-01-07
Abstract
Abstract A tungsten silicide reoxidation technique for forming a reoxidation layer in a CMOS MOSFET device. After forming an insulated gate member, which has a tungsten silicide layer overlying a polysilicon layer, a CVD oxide layer is deposited on the exposed and crystallized tungsten silicide layer to function as a cap prior to the formation of the reoxidation layer. The CVD oxide layer operates to slow the passage of oxygen atoms to combine with the tungsten atoms of the silicide layer but allows free migration of silicon atoms from the polysilicon layer to the tungsten silicide surface and combine with the oxygen atoms in forming a substantially planarized and uncontaminated reoxidation layer without the requirement of a substantially pure nitrogen ambient.
Inventors
- 👤 Been-Jon Woo
- 👤 Wei-Jen Lo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:42
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/663; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P95/00; Y; Y10; Y10S; Y10S148/00; Y10S148/118
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
216 words
A method of fabricating metal-oxide-semiconductor integrated circuit where a reoxidation layer is formed on an insulated gate member which overlies a substrate and in which said insulated gate member is comprised of a silicide layer overlying a polysilicon layer, comprising the steps of: (a) forming an oxidation insulating layer over opposite sides and upper surface of said gate member; (b) forming spacers abut said gate member; (c) etching said oxidation insulating layer to expose upper surface of said silicide layer of said gate member; (d) forming source and drain regions in said substrate; (e) forming a dielectric layer over said exposed upper surface of said silicide layer of said gate member, said dielectric layer having a thickness of at least 500 angstrom; (f) placing said device of step (e) in a furnace having a temperature of approximately 920° C.; (g) forming said reoxidation layer above said gate member by introducing oxygen into said furnace wherein oxygen atoms react with silicon atoms which are pulled free from said polysilicon layer to form said reoxidation layer, said reoxidation layer being substantially formed prior to said oxygen atoms penetrating said dielectric layer and said formed reoxidation layer to react with tungsten atoms of said silicide layer such that said reoxidation layer is formed having substantially planarized and uncontaminated surface.
Claim 2
Independent Claim
216 words
A method of fabricating metal-oxide-semiconductor integrated circuit where a reoxidation layer is formed on an insulated gate member which overlies a substrate and in which said insulated gate member is comprised of a silicide layer overlying a polysilicon layer, comprising the steps of: (a) forming an oxidation insulating layer over opposite sides and upper surface of said gate member; (b) forming spacers abut said gate member; (c) etching said oxidation insulating layer to expose upper surface of said silicide layer of said gate member; (d) forming source and drain regions in said substrate; (e) forming a dielectric layer over said exposed upper surface of said silicide layer of said gate member, said dielectric layer having a thickness of at least 500 angstrom; (f) placing said device of step (e) in a furnace having a temperature of approximately 920° C.; (g) forming said reoxidation layer above said gate member by introducing oxygen into said furnace wherein oxygen atoms react with silicon atoms which are pulled free from said polysilicon layer to form said reoxidation layer, said reoxidation layer being substantially formed prior to said oxygen atoms penetrating said dielectric layer and said formed reoxidation layer to react with tungsten atoms of said silicide layer such that said reoxidation layer is formed having substantially planarized and uncontaminated surface.
Claim 3
Dependent Claim
20 words
The method defined in claim 1 wherein said dieletric layer is comprised of a chemical vapor deposited low temperature oxide.
Claim 4
Dependent Claim
18 words
The method of claim 1 wherein said dielectric layer has a thickness of between 500 and 1000 angstroms.
Claim 5
Dependent Claim
18 words
The method of claim 2 wherein said dielectric layer has a thickness of between 500 and 1000 angstroms.
Claim 6
Dependent Claim
15 words
The method of claim 4 wherein said spacers are formed from a low temperature oxide.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-27 | 1992-03-28 | 1992-09-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-27 | 1996-03-28 | 1996-09-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-27 | 2000-03-28 | 2000-09-27 | $7700.00 | Window Closed / Lapsed |