Patent US5822256A successfully refreshed from Google Patents.
US5822256A
Expired / Lapsed
US
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Method and circuitry for usage of partially functional nonvolatile memory
Assignee: Intel Corp
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Filing: 1997-03-05
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Granted: 1998-10-13
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Expires: 2017-03-05
Abstract
Abstract A method and circuitry are described that permit one to utilize a partially functional integrated circuit memory. A memory array is segregated into separate blocks that can each be isolated to minimize the amount of the memory array rendered unusable by a defect. Circuitry is also provided to program memory cells within the array to one of at least three amounts of charge and thereby increase the amount of storage provided by the remaining functional blocks.
Inventors
- 👤 Mark E. Bauer
- 👤 Steven Wells
- 👤 David M. Brown
- 👤 Johnny Javanifard
- 👤 Sherif Sweha
- 👤 Robert N. Hasbun
- 👤 Gary J. Gallagher
- 👤 Mamun Rashid
- 👤 Rodney R. Rozman
- 👤 Glen Hawk
- 👤 George Blanchard
- 👤 Mark Winston
- 👤 Richard D. Pashley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:49
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/88; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C29/04; G11C29/08; G11C29/12; G11C29/44; G11C2211/00; G11C2211/56; G11C2211/564; G11C2211/5641
Claims Analysis
Total Claims: 56
Claim 1
Independent Claim
52 words
An apparatus comprising: a memory array having a plurality of blocks of multi-level memory cells; isolation circuitry, wherein the isolation circuitry disables any block containing defects; and multi-level cell circuitry that switches at least one non-defective block to a multiple bit per cell storage mode, if at least one block is disabled.
Claim 2
Independent Claim
52 words
An apparatus comprising: a memory array having a plurality of blocks of multi-level memory cells; isolation circuitry, wherein the isolation circuitry disables any block containing defects; and multi-level cell circuitry that switches at least one non-defective block to a multiple bit per cell storage mode, if at least one block is disabled.
Claim 3
Dependent Claim
29 words
The apparatus of claim 1 wherein each of the plurality of blocks has a separate power supply and the isolation circuitry disables the power supply of any defective block.
Claim 4
Dependent Claim
33 words
The apparatus of claim 1 wherein each of the plurality of blocks has a separate set of pitch limited cells and the isolation circuitry disables the pitch limited cells of any defective block.
Claim 5
Dependent Claim
13 words
The apparatus of claim 3 wherein the pitch limited cells are row drivers.
Claim 6
Dependent Claim
33 words
The apparatus of claim 1 wherein each of the plurality of blocks has a separate set of column selects and the isolation circuitry disables the set of column selects of any defective block.
Claim 7
Dependent Claim
51 words
The apparatus of claim 1 further comprising: redundant circuitry to be used in place of defective portions of the memory array, the isolation circuitry being used to isolate defective blocks by disabling only the blocks that contain defects and cannot be brought to full functionality by use of the redundant circuitry.
Claim 8
Dependent Claim
38 words
The apparatus as set forth in claim 1 wherein the multi-level cell circuitry switches each block between the multiple bit per cell storage mode and a single bit per cell storage mode on a block by block basis.
Claim 9
Dependent Claim
32 words
The apparatus as set forth in claim 1 wherein the multi-level cell circuitry collectively switches blocks between the multiple bit per cell storage mode and a single bit per cell storage mode.
Claim 10
Dependent Claim
22 words
The apparatus of claim 1 further comprising a block status register to indicate the defective blocks if there are any defective blocks.
Claim 11
Dependent Claim
19 words
The apparatus as set forth in claim 1 wherein the memory cells of the array are flash memory cells.
Claim 12
Dependent Claim
16 words
The apparatus of claim 10 wherein each of the plurality of blocks is an erase block.
Claim 13
Dependent Claim
13 words
The apparatus of claim 11 where each erase block has 512K memory cells.
Claim 14
Independent Claim
72 words
A method of utilizing a partially functional integrated circuit memory, the method comprising the steps of: a) partitioning an array of memory cells within the integrated circuit memory into a plurality of blocks; b) isolating defective blocks of the array such that any block that contains defects is disabled; and c) switching at least one non-defective block to a multiple bit per cell storage mode, if at least one block is disabled.
Claim 15
Independent Claim
72 words
A method of utilizing a partially functional integrated circuit memory, the method comprising the steps of: a) partitioning an array of memory cells within the integrated circuit memory into a plurality of blocks; b) isolating defective blocks of the array such that any block that contains defects is disabled; and c) switching at least one non-defective block to a multiple bit per cell storage mode, if at least one block is disabled.
Claim 16
Dependent Claim
33 words
The method of claim 13 wherein step b) further comprises the step of: disabling a power supply of any defective block, wherein each of the plurality of blocks has a separate power supply.
Claim 17
Dependent Claim
36 words
The method of claim 13 wherein step b) further comprises the step of: disabling pitch limited cells of any defective block, wherein each of the plurality of blocks has a separate set of pitch limited cells.
Claim 18
Dependent Claim
16 words
The method of claim 15 wherein the pitch limited cells that are disabled are row drivers.
Claim 19
Dependent Claim
34 words
The method of claim 13 wherein step b) other comprises the step of: disabling column selects of any defective blocks, wherein each of the plurality of blocks has a separate set of column selects.
Claim 20
Dependent Claim
37 words
The method of claim 13, wherein step b) further comprises the steps of: replacing defective portions of the memory array with redundant circuitry; and disabling a defective block only if the redundant circuitry cannot overcome a defect.
Claim 21
Dependent Claim
35 words
The method of claim 13 wherein the blocks are capable of being switched between a single bit per cell storage mode and the multiple bit per cell storage mode on a block by block basis.
Claim 22
Dependent Claim
28 words
The method of claim 13 wherein the non-defective blocks are collectively switched between a single bit per cell storage mode and the multiple bit per cell storage mode.
Claim 23
Dependent Claim
28 words
The method of claim 13 further comprising the step of: storing a block status indication for each defective block in a block status register of the memory array.
Claim 24
Dependent Claim
19 words
The method as set forth in claim 13 wherein the memory cells of the array are flash memory cells.
Claim 25
Dependent Claim
16 words
The method of claim 22 wherein each of the plurality of blocks is an erase block.
Claim 26
Dependent Claim
15 words
The method of claim 23 where each of the erase blocks has 512K memory cells.
Claim 27
Independent Claim
69 words
An apparatus comprising: a memory array having a plurality of blocks of multi-level memory cells; isolation circuitry, wherein the isolation circuitry disables any defective block; and multi-level cell circuitry that switches at least one non-defective block to a multiple bit per cell storage mode, if at least one block is disabled; and a processor coupled to the memory array to access at least one block that is not disabled.
Claim 28
Independent Claim
69 words
An apparatus comprising: a memory array having a plurality of blocks of multi-level memory cells; isolation circuitry, wherein the isolation circuitry disables any defective block; and multi-level cell circuitry that switches at least one non-defective block to a multiple bit per cell storage mode, if at least one block is disabled; and a processor coupled to the memory array to access at least one block that is not disabled.
Claim 29
Dependent Claim
29 words
The apparatus of claim 25 wherein each of the plurality of blocks has a separate power supply and the isolation circuitry disables the power supply of any defective block.
Claim 30
Dependent Claim
33 words
The apparatus of claim 25 wherein each of the plurality of blocks has a separate set of pitch limited cells and the isolation circuitry disables the pitch limited cells of any defective block.
Claim 31
Dependent Claim
13 words
The apparatus of claim 27 wherein the pitch limited cells are row drivers.
Claim 32
Dependent Claim
33 words
The apparatus of claim 25 wherein each of the plurality of blocks has a separate set of column selects and the isolation circuitry disables the set of column selects of any defective block.
Claim 33
Dependent Claim
51 words
The apparatus of claim 25 further comprising: redundant circuitry to be used in place of defective portions of the memory array, the isolation circuitry being used to isolate defective blocks by disabling only the blocks that contain defects and cannot be brought to full functionality by use of the redundant circuitry.
Claim 34
Dependent Claim
38 words
The apparatus as set forth in claim 25 wherein the multi-level cell circuitry switches each block between the multiple bit per cell storage mode and a single bit per cell storage mode on a block by block basis.
Claim 35
Dependent Claim
32 words
The apparatus as set forth in claim 25 wherein the multi-level cell circuitry collectively switches blocks between the multiple bit per cell storage mode and a single bit per cell storage mode.
Claim 36
Dependent Claim
22 words
The apparatus of claim 25 further comprising a block status register to indicate the defective blocks if there are any defective blocks.
Claim 37
Dependent Claim
19 words
The apparatus as set forth in claim 25 wherein the memory cells of the array are flash memory cells.
Claim 38
Dependent Claim
16 words
The apparatus of claim 32 wherein each of the plurality of blocks is an erase block.
Claim 39
Dependent Claim
13 words
The apparatus of claim 35 wherein each erase block has 512K memory cells.
Claim 40
Independent Claim
71 words
An apparatus comprising: a plurality of memory array dice disposed as a cluster on a wafer, at least one of the memory array dice comprising: a plurality of blocks of multi-level memory cells; isolation circuitry, wherein the isolation circuitry disables defective blocks; multi-level cell circuitry wherein the multi-level cell circuitry switches at least one non-defective block to a multiple bit per cell storage mode, if at least one block is disabled.
Claim 41
Independent Claim
71 words
An apparatus comprising: a plurality of memory array dice disposed as a cluster on a wafer, at least one of the memory array dice comprising: a plurality of blocks of multi-level memory cells; isolation circuitry, wherein the isolation circuitry disables defective blocks; multi-level cell circuitry wherein the multi-level cell circuitry switches at least one non-defective block to a multiple bit per cell storage mode, if at least one block is disabled.
Claim 42
Dependent Claim
29 words
The apparatus of claim 37 wherein each of the plurality of blocks has a separate power supply and the isolation circuitry disables the power supply of any defective block.
Claim 43
Dependent Claim
33 words
The apparatus of claim 37 wherein each of the plurality of blocks has a separate set of pitch limited cells and the isolation circuitry disables the pitch limited cells of any defective block.
Claim 44
Dependent Claim
13 words
The apparatus of claim 39 wherein the pitch limited cells are row drivers.
Claim 45
Dependent Claim
33 words
The apparatus of claim 37 wherein each of the plurality of blocks has a separate set of column selects and the isolation circuitry disables the set of column selects of any defective block.
Claim 46
Dependent Claim
57 words
The apparatus of claim 37 further comprising: redundant circuitry to be used in place of defective portions of the at least one of the memory array dice, the isolation circuitry being used to isolate defective blocks by disabling only the blocks that contain defects and cannot be brought to full functionality by use of the redundant circuitry.
Claim 47
Dependent Claim
38 words
The apparatus as set forth in claim 37 wherein the multi-level cell circuitry switches each block between the multiple bit per cell storage mode and a single bit per cell storage mode on a block by block basis.
Claim 48
Dependent Claim
32 words
The apparatus as set forth in claim 37 wherein the multi-level cell circuitry collectively switches block between the multiple bit per cell storage mode and a single bit pet cell storage mode.
Claim 49
Dependent Claim
22 words
The apparatus of claim 37 further comprising a block status register to indicate the defective blocks if there are any defective blocks.
Claim 50
Dependent Claim
26 words
The apparatus as set forth in claim 37 wherein the memory cells of the at least one of the memory array dice are flash memory cells.
Claim 51
Dependent Claim
16 words
The apparatus of claim 46 wherein each of the plurality of blocks is an erase block.
Claim 52
Dependent Claim
13 words
The apparatus of claim 47 wherein each erase block has 512K memory cells.
Claim 53
Dependent Claim
37 words
The apparatus of claim 37 wherein the wafer has a scribe region separating the plurality of memory array dice and at least two of the memory array dice are coupled by a bus within the scribe region.
Claim 54
Dependent Claim
29 words
The apparatus of claim 49 wherein at least one of the memory array dice can be bonded out separately if the cluster is cut apart along the scribe region.
Claim 55
Dependent Claim
26 words
The apparatus of claim 49 further comprising a controller die disposed within the cluster of the wafer, the controller die coordinating access to the memory cells.
Claim 56
Dependent Claim
29 words
The apparatus of claim 51 wherein at least one of the memory array dice can be bonded out separately if the cluster is cut apart along the scribe region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-12 | 2002-04-13 | 2002-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-12 | 2006-04-13 | 2006-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-12 | 2010-04-13 | 2010-10-13 | $7700.00 | Window Closed / Lapsed |