Row redundancy for flash memories

Claim 1

A memory array having a plurality of electrically programmable and electrically erasable memory cells each having a source region, a drain region, a floating gate and a control gate, the memory array comprising: a plurality of bit lines arranged in columns, each of the plurality of bit lines being coupled to the drain region of each of a number of the memory cells in one column; a first word line in a first row, the first word line being coupled to the control gate of each of a number of the memory cells in the first row; a second word line in a second row, the second word line being coupled to the control gate of each of a number of the memory cells in the second row; a third word line in a third row, the third word line being coupled to the control gate of each of a number of the memory cells in the third row; a fourth word line in a fourth row, the fourth word line being coupled to the control gate of each of a number of the memory cells in the fourth row; means for decoding row addresses and for selecting word lines, wherein if the first row is addressed for one of a read operation and a programming operation and if the first row is not functioning properly, the decoding means selects the third word line, and wherein if the second row is addressed for one of the read and programming operations and if the second row is not functioning properly, the decoding means selects the fourth word line, wherein during a preconditioning operation, if the first row is addressed and if the first row is not functioning properly, the decoding means selects the first word line and the second word line, wherein during the preconditioning operation, if the second row is addressed and if the second row is not functioning properly, the decoding means selects the third word line and the fourth word line; means for selecting a number of the plurality of bit lines and for coupling the source region of each of a number of the memory cells coupled to the selected bit lines to a first potential for one of the read and programming operations, and for coupling the source region of each of the memory cells to a second potential for an erasure operation.

Claim 5

A method of accessing alternate word lines in a memory array having a plurality of electrically programmable and electrically erasable memory cells each having a source region, a drain region, a floating gate and a control gate, the memory array comprising a plurality of bit lines arranged in columns, each of the plurality of bit lines being coupled to the drain region of each of a number of the memory cells in one column, the memory array further comprising a first word line coupled to the control gate of each of a number of the memory cells in a first row, a second word line coupled to the control gate of each of a number of the memory cells in a second row, a third word line coupled to the control gate of each of a number of the memory cells in a third row, and a fourth word line coupled to the control gate of each of a number of the memory cells in a fourth row, the method comprising the steps of: (A) selecting the third word line if the first row is addressed for one of a read operation and a programming operation and if the first row is not functioning properly; (B) selecting the fourth word line if the second row is addressed for one of the read and programming operations and if the second row is not functioning properly; (C) selecting the first and second word lines if the first row is addressed for a preconditioning operation and if the first row is not functioning properly; (D) selecting the third and fourth word lines if the second row is addressed for the preconditioning operation and if the second row is not functioning properly.

Claim 6

A method of accessing alternate word lines in a memory array having a plurality of electrically programmable and electrically erasable memory cells each having a source region, a drain region, a floating gate and a control gate, the memory array comprising a plurality of bit lines arranged in columns, each of the plurality of bit lines being coupled to the drain region of each of a number of the memory cells in one column, the memory array further comprising a first word line coupled to the control gate of each of a number of the memory cells in a first row, a second word line coupled to the control gate of each of a number of the memory cells in a second row, a third word line coupled to the control gate of each of a number of the memory cells in a third row, and a fourth word line coupled to the control gate of each of a number of the memory cells in a fourth row, the method comprising the steps of: (A) selecting the third word line if the first row is addressed for one of a read operation and a programming operation and if the first row is not functioning properly; (B) selecting the fourth word line if the second row is addressed for one of the read and programming operations and if the second row is not functioning properly; (C) selecting the first and second word lines if the first row is addressed for a preconditioning operation and if the first row is not functioning properly; (D) selecting the third and fourth word lines if the second row is addressed for the preconditioning operation and if the second row is not functioning properly.