Reset circuit for redundant memory using CAM cells

Claim 2

In a decoding scheme for redundant memory which includes a first content addressable memory (CAM) for decoding an address signal to access locations in said redundant memory, a reset circuit for resetting said first CAM, comprising: a second content addressable memory (CAM) configured to provide a state change at its output, wherein when voltage fluctuations which cause said first CAM to falsely latch-up are present, said second CAM will also be affected by said voltage fluctuations and will be forced to latch-up causing an output state change; and reset generation means for providing a reset signal to said first CAM and for detecting said output state change of said second CAM, said reset generation means communicatively coupled to receive said output state change from said second CAM and said reset generation means also communicatively coupled to said first CAM such that when said output state change is detected said reset signal causes said first CAM to be reset to prevent false latch-up by said first CAM.

Claim 3

The reset circuit of claim 1 wherein said reset signal is also coupled to reset said second CAM.

Claim 4

The reset circuit of claim 1 wherein said reset signal is also coupled to reset said second CAM, but said second CAM continues to provide said output state change as long as said false latch-up condition persists.

Claim 5

The reset circuit of claim 2 wherein said second CAM is made more sensitive to false latch-up conditions than said first CAM to ensure said second CAM to change its output state when said false latch-up condition occurs.

Claim 6

The reset circuit of claim 3 wherein said second CAM is made more sensitive to false latch-up conditions than said first CAM to ensure said second CAM to change its output state when said false latch-up condition occurs.

Claim 7

In a decoding scheme for a redundant memory which includes a plurality of first content addressable memories (CAMs) for decoding address signals to access locations in said redundant memory and wherein said first CAMs can falsely latch-up under voltage fluctuations or glitches, a reset circuit for resetting said first CAMs, comprising: a plurality of second CAMs, each configured to provide a state change at its output, wherein when said voltage fluctuations or glitches which cause said first CAMs to falsely latch-up occur, at least one of said second CAMs will also be forced to latch-up causing an output state change; gating means for providing a gated output when any one of said second CAMs generates said output state change, said gating means communicatively coupled to receive outputs from said plurality of second CAMs; and pulse generation means coupled to receive said gated output from said gating means and generating a reset pulse of a predetermined duration which is coupled to reset said first CAMs to prevent false latch-up by said first CAMs.

Claim 8

In a decoding scheme for a redundant memory which includes a plurality of first content addressable memories (CAMs) for decoding address signals to access locations in said redundant memory and wherein said first CAMs can falsely latch-up under voltage fluctuations or glitches, a reset circuit for resetting said first CAMs, comprising: a plurality of second CAMs, each configured to provide a state change at its output, wherein when said voltage fluctuations or glitches which cause said first CAMs to falsely latch-up occur, at least one of said second CAMs will also be forced to latch-up causing an output state change; gating means for providing a gated output when any one of said second CAMs generates said output state change, said gating means communicatively coupled to receive outputs from said plurality of second CAMs; and pulse generation means coupled to receive said gated output from said gating means and generating a reset pulse of a predetermined duration which is coupled to reset said first CAMs to prevent false latch-up by said first CAMs.

Claim 9

The reset circuit of claim 6 wherein said reset pulse is also coupled to reset said second CAMs.

Claim 10

The reset circuit of claim 6 wherein said reset pulse is also coupled to reset said second CAMs, but corresponding ones of said second CAMs continue to provide said output state changes as long as said false latch-up condition persists.

Claim 11

The reset circuit of claim 7 wherein some of said second CAMs are made more sensitive than said first CAMs to voltage glitches which cause false latch-up conditions to ensure at least one of said second CAMs to change its output state when said false latch-up condition occurs.

Claim 12

The reset circuit of claim 8 wherein said second CAMs are comprised of four separate CAMs, two of said second CAMs are made more sensitive to false latch-up conditions than said first CAMs to ensure at least one of said second CAMs to change its output state when said false latch-up condition occurs.

Claim 13

The reset circuit of claim 10 wherein two of said second CAMs are made more sensitive by having a smaller capacitor coupled to Vcc in one of said two CAMs and a larger capacitor coupled to Vss in the other of said two CAMs, said larger capacitor being larger in value than equivalent capacitors coupled to Vss in said first CAMs and said smaller capacitor being smaller in value than equivalent capacitors coupled to Vcc in said first CAMs.