US5046046A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Redundancy CAM using word line from memory
Assignee: Intel Corp
•
Filing: 1978-03-10
•
Granted: 1991-09-03
•
Expires: 1998-03-10
Abstract
Abstract A redundancy programming circuit employing a two EPROM cell CAM for storing programmed states of redundant elements. The CAMs are disposed aside a memory array and word lines of the array are extended to the CAMs for programming the CAMs. Two word lines are coupled to each EPROM cell so that programming can still be achieved in the event one of the lines is defective.
Inventors
- 👤 Sherif Sweha
- 👤 Mark Bauer
- 👤 Phil Kliza
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:09
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
122 words
A redundant memory circuit for a memory array comprising: a memory having a preselected number of rows and columns having addresses associated therewith, and one or more redundant rows or columns having initially unspecified addresses associated therewith; a redundancy decoder coupled to said memory for decoding addresses associated with said memory and activating said one or more redundant rows or columns if a selected location of said memory is defective; programming means coupled to said redundancy decoder for causing said redundant rows or columns having initially unspecified addresses associated therewith to be associated with addresses of said memory which are defective, wherein programming of said association is achieved by providing programming signals on one or more word lines having addresses associated therewith.
Claim 2
Dependent Claim
122 words
A redundant memory circuit for a memory array comprising: a memory having a preselected number of rows and columns having addresses associated therewith, and one or more redundant rows or columns having initially unspecified addresses associated therewith; a redundancy decoder coupled to said memory for decoding addresses associated with said memory and activating said one or more redundant rows or columns if a selected location of said memory is defective; programming means coupled to said redundancy decoder for causing said redundant rows or columns having initially unspecified addresses associated therewith to be associated with addresses of said memory which are defective, wherein programming of said association is achieved by providing programming signals on one or more word lines having addresses associated therewith.
Claim 3
Dependent Claim
18 words
The circuit of claim 1 further including means for disabling said locations of said memory which are defective.
Claim 4
Dependent Claim
24 words
The circuit of claim 2 wherein said programming means includes a content addressable memory for storing said locations of said memory which are defective.
Claim 5
Dependent Claim
152 words
In an integrated circuit memory device having a memory array, wherein word lines coupled to said array access said array and wherein a redundant memory circuit provides for redundant rows or columns in place of defective rows or columns of said memory array, a redundant programming circuit for providing locations of defective rows or columns of said memory array, comprising: a content addressable memory (CAM) coupled to said redundant memory circuit and to said memory array for storing locations of said defective rows or columns; said CAM comprised of memory cells which are coupled to at least one of said word lines of said memory array through a switching transistor, wherein programming for storing locations of said defective rows or columns is achieved by activating said at least one of said word lines in order to drive said switching transistor to couple a programming voltage to said memory cells of said CAM.
Claim 6
Dependent Claim
152 words
In an integrated circuit memory device having a memory array, wherein word lines coupled to said array access said array and wherein a redundant memory circuit provides for redundant rows or columns in place of defective rows or columns of said memory array, a redundant programming circuit for providing locations of defective rows or columns of said memory array, comprising: a content addressable memory (CAM) coupled to said redundant memory circuit and to said memory array for storing locations of said defective rows or columns; said CAM comprised of memory cells which are coupled to at least one of said word lines of said memory array through a switching transistor, wherein programming for storing locations of said defective rows or columns is achieved by activating said at least one of said word lines in order to drive said switching transistor to couple a programming voltage to said memory cells of said CAM.
Claim 7
Dependent Claim
20 words
The memory device of claim 4 wherein said CAM includes a latch for coupling an output from each memory cell.
Claim 8
Dependent Claim
17 words
The memory device of claim 5 wherein said memory cells are erasable programmable read-only memory (EPROM) cells.
Claim 9
Dependent Claim
17 words
The memory device of claim 5 wherein said memory cells are unerasable programmable read-only memory (UPROM) cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-02 | 1995-03-04 | 1995-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-02 | 1999-03-04 | 1999-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-02 | 2003-03-04 | 2003-09-03 | $7700.00 | Window Closed / Lapsed |