Defect-remediable semiconductor integrated circuit memory with spare substitution

Claim 2

A semiconductor integrated circuit memory comprising a memory array having a plurality of usual memory cells aranged in a matrix form of columns and rows, usual column (or row) select lines for selecting the columns (or rows) of said memory array, address line means for inputting an address signal, and a usual address transistor circuit connected between said address line means and each of said usual column (or row) select lines for accessing a selected one of said usual column (or row) select lines in accordance with said address signal, wherein said memory further comprises: a plurality of spare memory cells provided in the form of at least one column (or row) in said memory array; a spare column (or row) select line (304; 419, 420; 604; 704; 804) for selecting the column (or row) of said spare memory cells; a spare address transistor circuit (317-320; 411-413, 414-416; 715-718; 815-818) connected between said spare column (or row) select line and said address line means; a first converting circuit connected to said spare address transistor circuit and including first nonvolatile semiconductor memory-. ' element means (307-310; 402-403, 405-406; 607-610; 705-708; 805-808), said first converting circuit being operable upon the written or erased state of said first nonvolatile memory element means for conditioning said spare address transistor circuit into an active state to allow access to said spare column (or row) select line; and a second converting circuit connected to said spare column (or row) select line and including second nonvolatile semiconductor memory element means (306; 401, 404; 703; 803), said second converting circuit being operable upon the written or erased state of said second nonvolatile memory element means for setting said spare column (or row) select line to the grounded state.

Claim 3

A semiconductor integrated circuit memory as set forth in claim 1, wherein first nonvolatile memory elements in said first nonvolatile memory element means of said first converting circuit are connected to respective selected terminals of spare address transistors in said spare address transistor circuit, said first converting circuit being operable upon the written or erased states of said first nonvolatile memory elements for grounding predetermined ones of the selected terminals of said spare address transistors.

Claim 4

A semiconductor integrated circuit memory as set forth in claim 1, further comprising writing means for said first and second nonvolatile memory element means.

Claim 5

A semiconductor integrated circuit memory as set forth in claim 3, further comprising erasing means for said first and second nonvolatile memory element means.

Claim 6

A semiconductor integrated circuit memory as set forth in any one of claims 1 to 4, further comprising a third converting circuit connected to each of said usual column (or row) select lines and including third nonvolatile semiconductor memory element means (305; 407, 408; 502; 702; 802), said third converting .circuit being operable upon the written or erased state of said third nonvolatile memory elements means for grounding the associated usual column (or row) select line.

Claim 7

A semiconductor integrated circuit memory as set forth in claim 4, further comprising writing means for said third nonvolatile memory element means.

Claim 8

A semiconductor integrated circuit memory as set forth in claim 5, further comprising erasing means for said third nonvolatile memory element means.

Claim 9

A spare substitution method in a semiconductor integrated circuit memory comprising a memory array having a plurality of usuall memory cells arranged in a matrix form of columns and rows, usual column (or row) select lines for selecting the columns (or rows) of said memory array, address line means for inputting an address signal, address transistors connected between said address line means and each of said usual column (or row) select lines for accessing a selected one of said usual column (or row) select line in accordance with said address signal, a plurality of spare memory cells provided in the form of at least one column (or row) in said memory array, a spare column (or row) select line for selecting the column (or row) of said spare memory cells, spare address transistors connected between said spare column (or row) select line and said address line means, a first converting circuit connected to said spare address transistors and including first nonvolatile semiconductor memory element means, a second converting circuit connected to said spare column (or row) select line and including second nonvolatile semiconductor memory element means, and a third converting circuit connected to each of said usual column (or row) select lines and including third nonvolatile semiconductor memory element means, said method comprising the steps of: rendering-operative the third converting circuit connected to a defective one of said usual column (or row) select lines which includes a defective. usual memory cell, by setting the third nonvolatile memory element means into the written or erased state, thereby to ground the defective usual column (or row) select line; rendering operative the second converting circuit connected to said spare column (or row) select line, by setting the second nonvolatile memory elements into the written or erased state, thereby to release said spare column (or row) select line from its preliminarily grounded state; and rendering the first converting circuit operative by setting the first nonvolatile memory elements into the written or erased state, thereby to condition the spare address transistor corresponding to the usual address transistor of said defective usual column (or row) select line into an active state and to condition the other spare address transistor into an inactive state, whereby said spare column (or row) select line is substituted for said defective usual column (or row) select line.

Claim 10

A spare substitution method in a semiconductor integrated circuit memory comprising a memory array having a plurality of usuall memory cells arranged in a matrix form of columns and rows, usual column (or row) select lines for selecting the columns (or rows) of said memory array, address line means for inputting an address signal, address transistors connected between said address line means and each of said usual column (or row) select lines for accessing a selected one of said usual column (or row) select line in accordance with said address signal, a plurality of spare memory cells provided in the form of at least one column (or row) in said memory array, a spare column (or row) select line for selecting the column (or row) of said spare memory cells, spare address transistors connected between said spare column (or row) select line and said address line means, a first converting circuit connected to said spare address transistors and including first nonvolatile semiconductor memory element means, a second converting circuit connected to said spare column (or row) select line and including second nonvolatile semiconductor memory element means, and a third converting circuit connected to each of said usual column (or row) select lines and including third nonvolatile semiconductor memory element means, said method comprising the steps of: rendering-operative the third converting circuit connected to a defective one of said usual column (or row) select lines which includes a defective. usual memory cell, by setting the third nonvolatile memory element means into the written or erased state, thereby to ground the defective usual column (or row) select line; rendering operative the second converting circuit connected to said spare column (or row) select line, by setting the second nonvolatile memory elements into the written or erased state, thereby to release said spare column (or row) select line from its preliminarily grounded state; and rendering the first converting circuit operative by setting the first nonvolatile memory elements into the written or erased state, thereby to condition the spare address transistor corresponding to the usual address transistor of said defective usual column (or row) select line into an active state and to condition the other spare address transistor into an inactive state, whereby said spare column (or row) select line is substituted for said defective usual column (or row) select line.