US5813030A
Expired / Lapsed
US
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Cache memory system with simultaneous access of cache and main memories
Assignee: Hewlett Packard Development Co LP
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Filing: 1997-05-02
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Granted: 1998-09-22
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Expires: 2017-05-02
Abstract
Abstract A processing system includes a cache memory system which receives an address and a memory request from a processor. Simultaneously, information is accessed responsive to the address from a main memory and from a cache memory. During access of the information from the main memory and cache memory, it is determined whether the desired information is stored in the cache memory. If so, the information is output from the cache memory; if not, the information is output from the main memory.
Inventors
- 👤 Michael Eugene Tubbs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:20
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0877; G06F12/0884
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
179 words
A method of accessing information in a processing system, comprising the steps of: receiving a main memory address indicative of desired information stored in a main memory; simultaneously retrieving information at said main memory address from said main memory until a cache hit signal is received and retrieving information at a cache memory address corresponding to said main memory address; determining whether the desired information is stored within the cache memory during said simultaneously retrieving step; if the desired information is in the cache memory, outputting the information accessed from said cache memory upon a determination that the information is within said cache memory; if the desired information is not in the cache memory, waiting for a period of time: after the waiting step, updating one of a tag memory and a valid data memory associated with the cache memory; and outputting the desired information accessed from said main memory, wherein the period of time is of such a length to guarantee that the desired information output from the main memory will be valid immediately after the updating step.
Claim 2
Independent Claim
179 words
A method of accessing information in a processing system, comprising the steps of: receiving a main memory address indicative of desired information stored in a main memory; simultaneously retrieving information at said main memory address from said main memory until a cache hit signal is received and retrieving information at a cache memory address corresponding to said main memory address; determining whether the desired information is stored within the cache memory during said simultaneously retrieving step; if the desired information is in the cache memory, outputting the information accessed from said cache memory upon a determination that the information is within said cache memory; if the desired information is not in the cache memory, waiting for a period of time: after the waiting step, updating one of a tag memory and a valid data memory associated with the cache memory; and outputting the desired information accessed from said main memory, wherein the period of time is of such a length to guarantee that the desired information output from the main memory will be valid immediately after the updating step.
Claim 3
Dependent Claim
62 words
The method of claim 1 wherein said determining step comprises the steps: accessing a first tag from said tag memory responsive to a first predetermined portion of said main memory address; and comparing said first tag to a second tag comprising a second predetermined portion of said main memory address to determine whether said desired information is stored in the cache memory.
Claim 4
Dependent Claim
33 words
The method of claim 2 wherein said determining step further comprises accessing a valid data memory to determine whether the information stored in the cache memory at the cache memory address is valid.
Claim 5
Dependent Claim
35 words
The method of claim 3 wherein said step of updating said valid data memory comprises writing said second tag into said tag memory at an address based on said first predetermined portion of said address.
Claim 6
Dependent Claim
44 words
The method of claim 4 and further comprising writing the output of said main memory to said cache memory at an address specified by said first predetermined portion of said main memory address upon determination that the information is not within said cache memory.
Claim 7
Dependent Claim
19 words
The method of claim 2 and further comprising clearing the tag memory upon start up of the processing system.
Claim 8
Dependent Claim
50 words
The method of claim 6 and further comprising the step of setting at least one bit of said second tag to a predetermined value responsive to clearing the tag memory, such that said first and second tags are not equal during an initial access of said tag memory after clearing.
Claim 9
Dependent Claim
38 words
The method of claim 1 wherein said step of accessing information from said cache memory comprises the step of accessing information from said cache memory at an address specified by a predetermined portion of said main memory address.
Claim 10
Dependent Claim
174 words
A processing system comprising: a processor; a main memory coupled to said processor; a cache memory coupled to said processor and said main memory; and control circuitry, wherein said control circuitry is operable for simultaneously retrieving information from said main memory and said cache memory responsive to a memory request to a specified address by said processor; for determining whether information corresponding to the memory request is in said cache memory during retrieving information from of said main memory and said cache memory; for waiting for a period of time, then updating one of a tag memory and a valid data memory associated with the cache memory if the information is not in said cache memory wherein the period of time is of such a length to guarantee that the desired information output from the main memory will be valid immediately after the updating of one of the tag memory and the valid memory; and for terminating retrieving information from said main memory responsive to whether said memory request is in said cache memory.
Claim 11
Dependent Claim
174 words
A processing system comprising: a processor; a main memory coupled to said processor; a cache memory coupled to said processor and said main memory; and control circuitry, wherein said control circuitry is operable for simultaneously retrieving information from said main memory and said cache memory responsive to a memory request to a specified address by said processor; for determining whether information corresponding to the memory request is in said cache memory during retrieving information from of said main memory and said cache memory; for waiting for a period of time, then updating one of a tag memory and a valid data memory associated with the cache memory if the information is not in said cache memory wherein the period of time is of such a length to guarantee that the desired information output from the main memory will be valid immediately after the updating of one of the tag memory and the valid memory; and for terminating retrieving information from said main memory responsive to whether said memory request is in said cache memory.
Claim 12
Dependent Claim
68 words
The processing system of claim 9 wherein said control circuitry comprises: circuitry for accessing a first tag from said tag memory at a location corresponding to a first predetermined portion of said address; and circuitry for comparing said first tag to a second tag comprising a second predetermined portion of said address to determine whether information at the address in main memory is stored in the cache memory.
Claim 13
Dependent Claim
30 words
The processing system of claim 10 wherein said control circuitry further comprises: circuitry for accessing said valid data memory to determine whether information retrieved from the cache memory is valid.
Claim 14
Dependent Claim
38 words
The processing system of claim 10 wherein said circuitry for updating said valid data memory comprises circuitry for writing said second tag into said tag memory at a location corresponding to said first predetermined portion of said address.
Claim 15
Dependent Claim
24 words
The processing system of claim 10 wherein said control circuitry comprises circuitry for clearing the tag memory upon start up of the processing system.
Claim 16
Dependent Claim
51 words
The proessing system of claim 13 and further comprising the step of setting at least one bit of said second tag to a predetermined value responsive to clearing the tag memory, such that said first and second tags are not equal during an initial access of said tag memory after clearing.
Claim 17
Dependent Claim
48 words
The processing system of claim 9 wherein said control circuitry further comprises circuitry for writing an output from said main memory to said cache memory at a location corresponding to said first predetermined portion of said address upon determination that the information is not within said cache memory.
Claim 18
Dependent Claim
30 words
The processing system of claim 9 wherein said control circuitry comprises circuitry for retrieving information from said cache memory at a location corresponding to a predetermined portion of said address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-21 | 2002-03-23 | 2002-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-21 | 2006-03-23 | 2006-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-21 | 2010-03-23 | 2010-09-22 | $7700.00 | Window Closed / Lapsed |