EP0166341A2
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Multiprocessor system with fast path means for storage accesses
Assignee: International Business Machines Corp
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Filing: 1985-06-19
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Granted: —
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Expires: 2005-06-19
Abstract
Abstract A fast path (comprising control and data busses) directly connects between a storage controller (18) in a main storage (21) and a requestor (CPU). The fast path (12) is in parallel with the bus path (11, 16, 14) normally provided through the storage hierarchy between the requestor (CPU) and the storage controller (18). The fast path (12) may bypass intermediate levels in the storage hierarchy. The fast path (12) is used at least for fetch requests from the requestor (CPU), since fetch request have been found to comprise the majority of all storage access requests. System efficiency is significantly increased by using at least one fast path (12) in a system to decrease the peak loads on the normal path (11, 16, 14). A requestor (CPU) using the fast path (12) and to the normal path (11, 16, 14) in a system controller element (16). The request through the fast path (12) gets to the main storage (21) before the same request gets through the system controller element, but may be ignored by the storage (21) if the latter is busy. If accepted, the storage (21) can start its accessing controls sooner for a fast path request than if the request is received from the normal path. Every request must use controlled cross-interrogate (17) and storage protect (19) resources. Fast path request SP controls, the SCE priority controls, and by the storage element priority controls. When the accessed data is ready to be sent by the main storage (21), it can be sent to the requestor (CPU) faster on the fast path data bus (12) than on the SCE data bus (11,16,14). The fast path data bus (12) may be used to transfer data for requests ignored from the fast path.
Inventors
- 👤 George Louis Chiesa
- 👤 Matthew Anthony Krygowski
- 👤 Benedicto Umberto Messina
- 👤 Theodore Athanasios Papanastasiou
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 01:06
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
320 words
Multiprocessor system having plural central processing units, a system controller element for connecting the central processing units to a main storage controller which controls the access to a main storage, each central processing unit having a buffer control element for providing fetch and store requests from the central processing unit to the system controller element, the latter containing storage protection means and cross-interrogation means for checking for storage protection violations and any conflicting data in each other processor on each missed request in a cache directory, an input/output processor also being connected to the system controller element for providing input/output requests to the main storage controller, characterized by fast path bussing means (12) connected between said main storage controller (18) and the buffer control element (30) of the central processing units (CPU) for transferring fetch requests directly to the main storage controller (18); dual ports (96, 98) in the central processing units (CPU) respectively connected to the system controller element (16) and to the fast path bussing means (12) for simultaneously providing a fetch request to both, the system controller element (16) and to the fast path bussing means (12); main storage priority means (90) in the main storage controller (18) for receiving main storage requests from the fast path bussing means (12) and from the system controller element (16) for determining which request next accesses the main storage (21); system controller priority means (60) for receiving each storage request from one of the dual ports (96, 98) of the central processing units (CPU) and from the input/output processor (IOP) for determining which request the system controller element (16) will next provide to the main storage controller (18); and means (91, 41) for forcing the system controller element (16) to next handle a fetch request for storage protection violation checking in response to the system controller element (16) receiving a fast path accept signal from the main storage controller (18).
Claim 2
Dependent Claim
320 words
Multiprocessor system having plural central processing units, a system controller element for connecting the central processing units to a main storage controller which controls the access to a main storage, each central processing unit having a buffer control element for providing fetch and store requests from the central processing unit to the system controller element, the latter containing storage protection means and cross-interrogation means for checking for storage protection violations and any conflicting data in each other processor on each missed request in a cache directory, an input/output processor also being connected to the system controller element for providing input/output requests to the main storage controller, characterized by fast path bussing means (12) connected between said main storage controller (18) and the buffer control element (30) of the central processing units (CPU) for transferring fetch requests directly to the main storage controller (18); dual ports (96, 98) in the central processing units (CPU) respectively connected to the system controller element (16) and to the fast path bussing means (12) for simultaneously providing a fetch request to both, the system controller element (16) and to the fast path bussing means (12); main storage priority means (90) in the main storage controller (18) for receiving main storage requests from the fast path bussing means (12) and from the system controller element (16) for determining which request next accesses the main storage (21); system controller priority means (60) for receiving each storage request from one of the dual ports (96, 98) of the central processing units (CPU) and from the input/output processor (IOP) for determining which request the system controller element (16) will next provide to the main storage controller (18); and means (91, 41) for forcing the system controller element (16) to next handle a fetch request for storage protection violation checking in response to the system controller element (16) receiving a fast path accept signal from the main storage controller (18).
Claim 3
Dependent Claim
60 words
Multiprocessor system in accordance with claim 1, characterized by means (31B, 35B, 102, 103, 107...110) in said main storage controller (18) for selecting the fast path bussing means (12) for transmitting to the central processing units (CPU) data accessed in said main storage (21) for a storage request received by the system controller element (16) from the central processing unit.
Claim 4
Dependent Claim
54 words
Multiprocessor system in accordance with claim 2, characterized by fast path error detection means'(111) for detecting a failure in said fast path bussing means (12), and means (68, 74, 75, 112) for rejecting the fast path request with the request being forwarded from the dual port (96, 98) to the system controller element (16).
Claim 5
Dependent Claim
127 words
Multiprocessor system in accordance with claim 1, characterized by main storage request cancelling means (60, 72) in the system controller element (16) for sending a cancelling signal to the main storage (21) for cancelling any transmission of accessed data for the fetch request in response to an adverse determination for the fetch request by the cross-interrogate circuits (17) or by the storage protect means 19 in the system controller element (16); and by fast path selection means (30, 31B...35B, 90, 121, 122) in the main storage controller (18) for selecting the fast path bussing means (12) for directly transmitting to the central processing unit (CPU) data accessed in said main storage (21) when no adverse determination occurs in the system controller element (16) for the fetch request.
Claim 6
Dependent Claim
174 words
Multiprocessor system in accordance with claim 1, characterized by the fast path bussing means (12) connecting only one of the central processing units (CPU) to the main storage controller (18) and receiving each fetch request from said one central processing unit (CPU) when that fetch request is provided to the system common path (11, 16, 14), by main storage acceptance means (90, 91, 60) providing a main storage accept signal on a line (91) to the system common path (11, 16, 14) indicating that the requested data will be transmitted to the said one central processing unit (CPU) on the fast path bussing means (12) in order to enable the system common path (11, 16, 14) to transfer data for another request from any other central processing unit (CPU), and by inhibit means (74, 75, 121, 122) for inhibiting the main storage priority means (90) from accepting another request from the fast path bussing means (12) until the requested data have been found not to have been updated in another central processing unit (CPU).
Claim 7
Dependent Claim
141 words
Multiprocessor system in accordance with claim 1, characterized in that subsets of said central processing units (CPU(1)...CPU(N-2); CPU'(1)...CPU'(N-2)) are each connected to a local main storage controller (18(0), 18(1)), via a local system controller element (16(0), 16(1)) dedicated to said subset, the system controller elements (16(0), 16(1)) being interconnected among themselves by busses (20) containing cross-interrogation lines, request lines and data dlines, and each having a connection to each remote main storage controller (18(1), 18(0)), that each central processing unit (CPU(1)... CPU(N-2); CPU'(1)...CPU'(N-2)) and each input/output processor (IOP, IOP') associated with that subset has fast path bussing means (12 (1)...12 (N-2), 12(N+1)) directly connected to the subset's respective main storage controller (18(0), 18(1)), the connection between said local system control elements (16(0), 16(1)) and said remote main storage controllers (18(1), 18(0)) also being designed as fast path bussing means (FP(N), FP'(N)).
References Cited (Backward Citations)
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