Write-back cache system using concurrent address transfers to setup requested address in main memory before dirty miss signal from cache

Claim 1

In a computer system comprising a central processing unit (CPU), a write-back cache memory unit (cache) having a data store and a comparator for indicating whether information requested by the CPU from the cache is a hit, a clean miss, or a dirty miss, and a main memory unit (main memory), said units coupled so that the main memory can communicate only with the cache and so that the CPU can fetch information from and store information to the main memory only via the cache, and further coupled so that state machines representing the states of the cache and the main memory, respectively, are linked together, a method comprising the steps of: (a) simultaneously sending an address of information desired to be read from the cache by the CPU from the CPU to both the cache and main memory at such a time that said address is set up in the main memory prior to receiving a dirty miss indication from the comparator; (b) fetching the encached copy of said information from the data store and then temporarily buffering the fetched information in the computer system prior to receiving said dirty miss indication from said comparator; and, (c) storing a copy of the desired information fetched from the main memory into the cache if either a clean or dirty miss indication is provided by the comparator; wherein step (c) takes place before dirty information buffered in the system is written back to the main memory if the comparator provides a dirty miss indication.