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US4586133A
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Multilevel controller for a cache memory interface in a multiprocessing system
Assignee: Unisys Corp
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Filing: 1983-04-05
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Granted: 1986-04-29
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Expires: 2003-04-05
Abstract
Abstract A two-level controller for a system interface between an auxiliary processor and main memory modules of a multiprocessing system which respective processor and system have different clock rates, memory access times and memory addressing capabilities. The two-level controller is formed of a hierarchy of two control stores wherein the receipt of a command code by the first control store from the processor causes it to address the second control store. Each control store is provided with program counter means to receive its respective address and to increment that address until it receives a new address so as to asynchronously control simultaneous operation of a memory interface to said memory modules and a cache mechanism coupled to the processor.
Inventors
- 👤 Thomas M. Steckler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 13:34
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855; G06F12/0859
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
225 words
A system interface unit for asynchronous control of transmission of data and code between a processor and a main memory system, said interface unit comprising: memory interface means coupled to said main memory system for transmitting data and code to and receiving data and code from said memory system; cache mechanism means coupled to said processor and to said memory interface means for storing data and code received from said main memory system for access by said processor; and a first control store and a second control store each having output means coupled to said cache mechanism means and said memory interface means respectively to provide control signals thereto; to independently control the simultaneous operation of said memory interface means and said cache mechanism means; said first control store having an input means being coupled to receive a command code from said processor as at least a part of an address, said first control store supplying, in response to said command code, a second command code to address said second control store, said second control store having an input means being coupled to said first control store output means; each control store input means being provided with program counter means for simultaneous operation of said respective control stores by incrementing a previous address to address the respective control store unless a new address is received.
Claim 2
Independent Claim
225 words
A system interface unit for asynchronous control of transmission of data and code between a processor and a main memory system, said interface unit comprising: memory interface means coupled to said main memory system for transmitting data and code to and receiving data and code from said memory system; cache mechanism means coupled to said processor and to said memory interface means for storing data and code received from said main memory system for access by said processor; and a first control store and a second control store each having output means coupled to said cache mechanism means and said memory interface means respectively to provide control signals thereto; to independently control the simultaneous operation of said memory interface means and said cache mechanism means; said first control store having an input means being coupled to receive a command code from said processor as at least a part of an address, said first control store supplying, in response to said command code, a second command code to address said second control store, said second control store having an input means being coupled to said first control store output means; each control store input means being provided with program counter means for simultaneous operation of said respective control stores by incrementing a previous address to address the respective control store unless a new address is received.
Claim 3
Dependent Claim
42 words
A system interface unit according to claim 1 wherein: said cache mechanism includes a random access memory having two sections, one for code segments and one for data segments, said sections being divided into a plurality of groups of said respective segments.
Claim 4
Dependent Claim
60 words
A system interface unit according to claim 2 including: an address register coupled to said processor to receive a memory address, said address being divided into a word identification field, a group address and a segment address; and a table of locations coupled to said address register to receive segment identification fields of segments stored in said random access memory.
Claim 5
Dependent Claim
56 words
A system interface unit according to claim 3 further including: comparison detection means coupled to said address register and to said table of locations to compare word identification fields in said table with the word identification field of an address received by said address register and to signal said first control store when a comparison occurs.
Claim 6
Dependent Claim
39 words
A system interface unit according to claim 1 wherein: said main memory system includes a plurality of memory units; and said memory interface means includes bus interface means coupled between said cache mechanism and said plurality of memory units.
Claim 7
Dependent Claim
42 words
A system interface unit according to claim 5 further including: a bus coupling said bus interface means to said cache mechanism means; and a bypass register coupled between said memory bus interface means and said processor to bypass the cache mechanism means.
Claim 8
Dependent Claim
39 words
A system interface unit according to claim 1 wherein: said second control store is coupled to said first control store to signal said first control store of the availability of the second control store to receive a command code.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-28 | 1989-10-28 | 1990-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-28 | 1993-10-28 | 1994-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-28 | 1997-10-28 | 1998-04-29 | $7700.00 | Window Closed / Lapsed |