US5812477A
Expired / Lapsed
US
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Antifuse detection circuit
Assignee: Micron Technology Inc
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Filing: 1996-10-03
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Granted: 1998-09-22
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Expires: 2016-10-03
Abstract
Abstract An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The circuit accurately detects an antifuse which has a relatively high resistance after being programmed.
Inventors
- 👤 Stephen L. Casper
- 👤 Chris G. Martin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:49
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/18
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
118 words
An antifuse detection circuit comprising: first and second antifuses, each antifuse having a first node connected to a common reference voltage, and a second node connected to a latch circuit; and the latch circuit comprising first and second cross-coupled p-channel transistors, a drain of the first and second p-channel transistors is connected to a second reference voltage, a source of the first p-channel transistor is coupled to a gate of the second p-channel transistor, a source of the second p-channel transistor is coupled to a gate of the first p-channel transistor, the first antifuse is coupled to the source of the first p-channel transistor, and the second antifuse is coupled to the source of the second p-channel transistor.
Claim 2
Dependent Claim
118 words
An antifuse detection circuit comprising: first and second antifuses, each antifuse having a first node connected to a common reference voltage, and a second node connected to a latch circuit; and the latch circuit comprising first and second cross-coupled p-channel transistors, a drain of the first and second p-channel transistors is connected to a second reference voltage, a source of the first p-channel transistor is coupled to a gate of the second p-channel transistor, a source of the second p-channel transistor is coupled to a gate of the first p-channel transistor, the first antifuse is coupled to the source of the first p-channel transistor, and the second antifuse is coupled to the source of the second p-channel transistor.
Claim 3
Dependent Claim
80 words
The antifuse detection circuit of claim 1 further comprising: first n-channel transistor having a drain connected to the gate of the second p-channel transistor, a source connected to the first node of the first antifuse, and a gate connected to receive a bias voltage; and second n-channel transistor having a drain connected to the gate of the first p-channel transistor, a source connected to the first node of the second antifuse, and a gate connected to receive the bias voltage.
Claim 4
Dependent Claim
72 words
The antifuse detection circuit of claim 1 further comprising: third p-channel transistor having a drain connected to the source of the first p-channel transistor, a source coupled to the first antifuse, and a gate connected to receive a bias voltage; and fourth p-channel transistor having a drain connected to the source of the second p-channel transistor, a source coupled to the second antifuse, and a gate connected to receive the bias voltage.
Claim 5
Dependent Claim
25 words
The antifuse detection circuit of claim 1 further comprising: programming circuitry connected to the first and second antifuses for selectively programming one of the antifuses.
Claim 6
Independent Claim
80 words
A method of detecting a programed antifuse, the method comprising the steps of: programming a first antifuse to create a conductive path between first and second conductive plates; coupling the first conductive plate to a first reference voltage; coupling the second conductive plate to a latch circuit; coupling a first conductive plate of an un-programmed second antifuse to the first reference voltage; coupling a second conductive plate of the second antifuse to the latch circuit; and activating the latch circuit.
Claim 7
Independent Claim
80 words
A method of detecting a programed antifuse, the method comprising the steps of: programming a first antifuse to create a conductive path between first and second conductive plates; coupling the first conductive plate to a first reference voltage; coupling the second conductive plate to a latch circuit; coupling a first conductive plate of an un-programmed second antifuse to the first reference voltage; coupling a second conductive plate of the second antifuse to the latch circuit; and activating the latch circuit.
Claim 8
Dependent Claim
16 words
The method of claim 5 wherein the latch circuit comprises a pair of cross-coupled p-channel transistors.
Claim 9
Dependent Claim
53 words
The method of claim 5 wherein the step of programming a first antifuse comprises the steps of: electrically isolating the first antifuse from the latch circuit; and providing a voltage across the first and second conductive plates having a potential difference sufficient to create the conductive path between first and second conductive plates.
Claim 10
Independent Claim
66 words
A method of repairing a memory device, the method comprising the steps of: detecting a defective primary circuit; selectively programing an antifuse; coupling the antifuse between a reference voltage and a latch circuit; coupling an un-programmed second antifuse to the reference voltage and the latch circuit; activating the latch circuit to detect the programmed antifuse; and enabling a redundant circuit to replace the defective primary circuit.
Claim 11
Independent Claim
66 words
A method of repairing a memory device, the method comprising the steps of: detecting a defective primary circuit; selectively programing an antifuse; coupling the antifuse between a reference voltage and a latch circuit; coupling an un-programmed second antifuse to the reference voltage and the latch circuit; activating the latch circuit to detect the programmed antifuse; and enabling a redundant circuit to replace the defective primary circuit.
Claim 12
Dependent Claim
26 words
The antifuse detection circuit of claim 1 further comprising: antifuse programming circuitry connected to the first and second antifuses for selectively programming one of the antifuses.
Claim 13
Dependent Claim
158 words
The antifuse detection circuit of claim 9 wherein the antifuse programming circuitry comprises: a first isolation transistor connected to the first node of the first antifuse to isolate the first node from the reference voltage; a first programming transistor having a drain adapted to receive a program voltage and a source connected to the first node of the first antifuse; a second programing transistor having a drain connected to the second node of the first antifuse, and a source connected to receive the reference voltage; a second isolation transistor connected to the first node of the second antifuse to isolate the first node from the reference voltage; a third programming transistor having a drain adapted to receive a program voltage and a source connected to the first node of the second antifuse; and a fourth programing transistor having a drain connected to the second node of the second antifuse, and a source connected to receive the reference voltage.
Claim 14
Dependent Claim
128 words
A memory device comprising: an array of memory cells; and an antifuse detection circuit comprising, first and second antifuses, each antifuse having a first node connected to a common reference voltage, and a second node connected to a latch circuit, and the latch circuit comprising first and second cross-coupled p-channel transistors, a drain of the first and second p-channel transistors is connected to a second reference voltage, a source of the first p-channel transistor is coupled to a gate of the second p-channel transistor, a source of the second p-channel transistor is coupled to a gate of the first p-channel transistor, the first antifuse is coupled to the source of the first p-channel transistor, and the second antifuse is coupled to the source of the second p-channel transistor.
Claim 15
Dependent Claim
128 words
A memory device comprising: an array of memory cells; and an antifuse detection circuit comprising, first and second antifuses, each antifuse having a first node connected to a common reference voltage, and a second node connected to a latch circuit, and the latch circuit comprising first and second cross-coupled p-channel transistors, a drain of the first and second p-channel transistors is connected to a second reference voltage, a source of the first p-channel transistor is coupled to a gate of the second p-channel transistor, a source of the second p-channel transistor is coupled to a gate of the first p-channel transistor, the first antifuse is coupled to the source of the first p-channel transistor, and the second antifuse is coupled to the source of the second p-channel transistor.
Claim 16
Dependent Claim
36 words
The memory device of claim 11 further comprising: redundant circuitry coupled to the array of memory cells and the control circuitry, and adapted to enable redundant memory cells in response to the first and second antifuses.
Claim 17
Dependent Claim
25 words
The memory device of claim 11 further comprising antifuse programming circuitry connected to the first and second antifuses for selectively programming one of the antifuses.
Claim 18
Dependent Claim
157 words
The memory device of claim 13 wherein the antifuse programming circuitry comprises: a first isolation transistor connected to the first node of the first antifuse to isolate the first node from the reference voltage; a first programming transistor having a drain adapted to receive a program voltage and a source connected to the first node of the first antifuse; a second programing transistor having a drain connected to the second node of the first antifuse, and a source connected to receive the reference voltage; a second isolation transistor connected to the first node of the second antifuse to isolate the first node from the reference voltage; a third programming transistor having a drain adapted to receive a program voltage and a source connected to the first node of the second antifuse; and a fourth programing transistor having a drain connected to the second node of the second antifuse, and a source connected to receive the reference voltage.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-09-21 | 2002-03-23 | 2002-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-21 | 2006-03-23 | 2006-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-21 | 2010-03-23 | 2010-09-22 | $7700.00 | Window Closed / Lapsed |