US5440246A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable circuit with fusible latch
Assignee: Promos Technologies Inc
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Filing: 1994-03-22
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Granted: 1995-08-08
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Expires: 2014-03-22
Abstract
Abstract A logical latch is permanently programmable to a selected state for use as a control circuit with extremely low power consumption in an integrated circuit.
Inventors
- 👤 Michael A. Murray
- 👤 Li-Chun Li
- 👤 Hsing T. Tuan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:01
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
174 words
A programmable logical latch circuit for controlling another circuit, comprising: a first output lead and a second output lead; a first fuse having a first terminal coupled to a supply voltage terminal and a second terminal coupled to said first output lead; a first transistor of a first conductivity type having a first terminal coupled to said first output lead, a second terminal coupled to ground, and a gate coupled to said second output lead; a second fuse having a first terminal coupled to said second output lead and a second terminal coupled to ground; and a second transistor of a second conductivity type; having a first terminal coupled to said supply voltage terminal, a second terminal coupled to said second output lead, and a gate coupled to said first output lead; wherein said logical latch circuit, without any additional circuitry being required, is capable of assuming a first state if both said first and second fuses are intact and of assuming a second state if both said first and second fuses are opened.
Claim 2
Dependent Claim
174 words
A programmable logical latch circuit for controlling another circuit, comprising: a first output lead and a second output lead; a first fuse having a first terminal coupled to a supply voltage terminal and a second terminal coupled to said first output lead; a first transistor of a first conductivity type having a first terminal coupled to said first output lead, a second terminal coupled to ground, and a gate coupled to said second output lead; a second fuse having a first terminal coupled to said second output lead and a second terminal coupled to ground; and a second transistor of a second conductivity type; having a first terminal coupled to said supply voltage terminal, a second terminal coupled to said second output lead, and a gate coupled to said first output lead; wherein said logical latch circuit, without any additional circuitry being required, is capable of assuming a first state if both said first and second fuses are intact and of assuming a second state if both said first and second fuses are opened.
Claim 3
Dependent Claim
28 words
A logical latch circuit as in claim 1 wherein said first and second fuses comprise polysilicon fuses which are capable of being open circuited by a laser pulse.
Claim 4
Dependent Claim
24 words
A logical latch circuit as in claim 2 wherein said first conductivity type comprises N-type conductivity and said second conductivity type comprises P-type conductivity.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-07 | 1999-02-06 | 1999-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-07 | 2003-02-06 | 2003-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-07 | 2007-02-06 | 2007-08-08 | $7700.00 | Window Closed / Lapsed |