Data latch circuit having non-volatile memory cell

Claim 2

A data latch circuit for selectively varying the threshold voltage of a non-volatile memory cell in accordance with data to be stored, and latching data on the basis of whether the non-volatile memory cell is in on-state or off-state, characterized by comprising: a non-volatile memory cell (11) having a writing transistor (T3) and a reading transistor (T4), and disposed to store data, the writing and reading transistors (T3, T4) having at least one control gate (CG or CG3, CG4) and a common floating gate (FG), the reading transistor (T4) having a threshold voltage lower than the writing transistor (T3), the control gate (CG or CG4) of the reading transistor (T4) being disposed to be supplied, during normal operation, with a constant voltage independent from a power supply voltage; and latch means (60) for latching potentials corresponding to the on- and off-states of the non-volatile memory cell (11).

Claim 3

The data latch circuit according to claim 1, characterized in that the writing transistor (T3) is of an enhancement type, and the reading transistor (T4) is of a depletion type.

Claim 4

The data latch circuit according to claim 1, characterized in that the non-volatile memory cell (11) consists of an erasable/programmable read only memory, and the reading transistor (T4) is made to be of a depletion type by ion implantation in an initial state assumed before data is written therein.

Claim 5

The data latch circuit according to claim 1, characterized in that the non-volatile memory cell (11) consists of an electrical erasable/programmable read only memory, and the reading transistor (T4) is made to be of a depletion type by erasion for initialization.

Claim 6

The data latch circuit according to claim 1, characterized in that the constant voltage, independent from the power supply voltage applied to the control gate of the reading transistor (T4) during normal operation, is a ground potential (Vss).

Claim 7

The data latch circuit according to claim 1, characterized in that the writing and reading transistors (T3, T4) have a common control gate (CG).

Claim 8

The data latch circuit according to claim 1, characterized in that the reading and writing transistors (T3, T4) have their respective control gates (CG3, CG4), and the control gate (CG4) of the reading transistor (CT4) is connected to a ground terminal (Vss).

Claim 9

The data latch circuit according to claim 1, characterized by further comprising a stress-relaxing transistor (T2) having a current path, one end of which is connected to an end of the current path of the reading transistor (T4), and the other end of which is connected to the latch means (60).

Claim 10

The data latch circuit according to claim 1, characterized by further comprising a write control transistor (T5) which has a current path connected between the drain of the writing transistor (T3) and a power supply (Vpp) used for writing, and also has a gate to be supplied with the power supply voltage for writing at the time of writing and to be supplied with a ground potential (Vss) at the time of other than writing.

Claim 11

The data latch circuit according to claim 1, characterized in that the latch means (60) includes a CMOS inverter circuit (IV1), and a p-channel MOS transistor (T1) for performing feedback control, which has a source connected to a power supply (Vcc), a drain connected to the input node of the CMOS inverter circuit (IV1), and a gate connected to the output node of the CMOS inverter circuit (IV1).

Claim 12

The data latch circuit according to claim 10, characterized by further comprising a capacitor (C1) connected between the input node of the CMOS inverter circuit (IV1) and the power supply (Vcc).

Claim 13

The data latch circuit according to claim 1, characterized by further comprising selector means (62) responsive to the output of the latch means (60) for selecting one of an address signal (Adi) and an inverted signal (Adi) of the address signal.

Claim 14

A data latch circuit for selectively varying the threshold voltage of a non-volatile memory cell in accordance with data to be stored, and latching data on the basis of whether the non-volatile memory cell is in an on-state or off-state, characterized by comprising: a first non-volatile memory cell (11 a) having a first writing transistor (T3a) and a first reading transistor (T4a), and disposed to store data, the first writing and reading transistors (T3a, T4a) having at least one first control gate and a first common floating gate, the first reading transistor (T4a) having a threshold voltage lower than the first writing transistor (T3a), the control gate of the first reading transistor (T4a) being disposed to be supplied, during normal operation, with a constant voltage independent from a power supply voltage; a second non-volatile memory cell (11 b) having a second writing transistor (T3b) and a second reading transistor (T4b), and disposed to store complementary data with respect to data to be stored in the first non-volatile memory cell (11 a), the second writing and reading transistors (T3b, T4b) having at least one second control gate and a second common floating gate, the second reading transistor (T4b) having a threshold voltage lower than the second writing transistor (T3b), the control gate of the second reading transistor (T4b) being disposed to be supplied, during normal operation, with the constant voltage; and latch means (T6a, T6b, 41, 42) for latching potentials corresponding to the on- and off-states of the first and second non-volatile memory cells (11 a, 11 b).

Claim 15

A data latch circuit for selectively varying the threshold voltage of a non-volatile memory cell in accordance with data to be stored, and latching data on the basis of whether the non-volatile memory cell is in an on-state or off-state, characterized by comprising: a first non-volatile memory cell (11 a) having a first writing transistor (T3a) and a first reading transistor (T4a), and disposed to store data, the first writing and reading transistors (T3a, T4a) having at least one first control gate and a first common floating gate, the first reading transistor (T4a) having a threshold voltage lower than the first writing transistor (T3a), the control gate of the first reading transistor (T4a) being disposed to be supplied, during normal operation, with a constant voltage independent from a power supply voltage; a second non-volatile memory cell (11 b) having a second writing transistor (T3b) and a second reading transistor (T4b), and disposed to store complementary data with respect to data to be stored in the first non-volatile memory cell (11 a), the second writing and reading transistors (T3b, T4b) having at least one second control gate and a second common floating gate, the second reading transistor (T4b) having a threshold voltage lower than the second writing transistor (T3b), the control gate of the second reading transistor (T4b) being disposed to be supplied, during normal operation, with the constant voltage; and latch means (T6a, T6b, 41, 42) for latching potentials corresponding to the on- and off-states of the first and second non-volatile memory cells (11 a, 11 b).

Claim 16

The data latch circuit according to claim 13, characterized in that the latch means includes a flip-flop circuit (FF).

Claim 17

The data latch circuit according to claim 14, characterized in that the flip-flop circuit (FF) includes first and second p-channel MOS transistors (T6a, T6b), the first p-channel MOS transistor (T6a) having a gate connected to the drain of the second p-channel MOS transistor (T6b), and a drain connected to the gate of the same, the first and second p-channel MOS transistors (T6a, T6b) serving as the loads of first and second reading transistors (T4a, T4b), respectively.

Claim 18

The data latch circuit according to claim 15, characterized by further comprising: a first stress-relaxing transistor (T2a) having a current path, one end of which is connected to an end of the current path of the first reading transistor (T4a), and the other end of which is connected to the first p-channel MOS transistor (T6a), and a gate connected to a ground terminal (Vss); and a second stress-relaxing transistor (T2b) having a current path, one end of which is connected to an end of the current path of the second reading transistor (T4b), and the other end of which is connected to the second p-channel MOS transistor (T6b), and a gate connected to the ground terminal (Vss).

Claim 19

The data latch circuit according to claim 13, characterized by further comprising: a first write control transistor (T5a) which has a current path connected between the drain of the first writing transistor (T3a) and a power supply (Vpp) used for writing, and also has a gate to be supplied with a power supply voltage (Vpp) for writing at the time of writing and to be supplied with a ground potential (Vss) at the time of other than writing; and a second write control transistor (T5b) which has a current path connected between the drain of the second writing transistor (T3b) and the power supply (Vpp) used for writing, and also has a gate to be supplied with the power supply voltage (Vpp) for writing at the time of writing and to be supplied with the ground potential (Vss) at the time of other than writing.

Claim 20

The data latch circuit according to claim 13, characterized by further comprising selector means (62) responsive to the output of the latch means (T6a, T6b, 41, 42) for selecting one of an address signal (Adi) and an inverted signal (Adi) of the address signal.

Claim 21

A data latch circuit for selectively varying the threshold voltage of a non-volatile memory cell in accordance with data to be stored, and latching data on the basis of whether the non-volatile memory cell is in an on-state or off-state, characterized by comprising: a non-volatile memory cell (11) having a writing transistor (T3) and a reading transistor (T4), and disposed to store data, the writing and reading transistors (T3, T4) having at least one control gate and a common floating gate, the reading transistor (T4) having a threshold voltage lower than the writing transistor (T3), the control gate of the reading transistor being disposed to be supplied, during normal operation, with a constant voltage independent from a power supply voltage; an external terminal (51); and output means (52, 53, 54, 55) for outputting from the external terminal (51) potentials corresponding to the on- and off-states of the non-volatile memory cell (11).

Claim 22

A data latch circuit for selectively varying the threshold voltage of a non-volatile memory cell in accordance with data to be stored, and latching data on the basis of whether the non-volatile memory cell is in an on-state or off-state, characterized by comprising: a non-volatile memory cell (11) having a writing transistor (T3) and a reading transistor (T4), and disposed to store data, the writing and reading transistors (T3, T4) having at least one control gate and a common floating gate, the reading transistor (T4) having a threshold voltage lower than the writing transistor (T3), the control gate of the reading transistor being disposed to be supplied, during normal operation, with a constant voltage independent from a power supply voltage; an external terminal (51); and output means (52, 53, 54, 55) for outputting from the external terminal (51) potentials corresponding to the on- and off-states of the non-volatile memory cell (11).

Claim 23

The data latch circuit according to claim 19, characterized in that the output means includes first load means (53, 54, 55) connected between the external terminal (51) and one end of the current path of the reading transistor (T4), and second load means (52, 55) connected between a power supply (Vcc) and the one end of the current path of the reading transistor (T4).

Claim 24

The data latch circuit according to claim 19, characterized by further comprising a stress-relaxing transistor (T2) having a current path, one end of which is connected to the other end of the current path of the reading transistor (T4), and the other end of which is connected to a power supply (Vcc), and also having a gate connected to a ground terminal (Vss).

Claim 25

The data latch circuit according to claim 1, characterized by further comprising a write control transistor (T5) which has a current path connected between the drain of the writing transistor (T3) and a power supply (Vpp) used for writing, and also has a gate to be supplied with a power supply voltage (Vpp) for writing at the time of writing and to be supplied with a ground potential (Vss) at the time of other than writing.