Nonvolatile semiconductor memory device and a method of making the same

Claim 2

A nonvolatile semiconductor memory device including a plurality of memory cells, each of said memory cells including a MOS type field-effect transistor having a floating gate, said semiconductor memory device comprising: a semiconductor substrate; an element-isolation structure formed on a surface of said semiconductor substrate so as to define a plurality of element regions, each of said element regions being defined between at least two linear portions, which extend in parallel to a longitudinal direction, of said element-isolation structure; each of said MOS transistors being formed in one of said element regions and including a gate oxide film formed on the surface of said semiconductor substrate and having tunneling oxide films at both end portions of said gate oxide film, each of said MOS transistors further including a pair of impurity diffusion layers constituting its source and drain, respectively, formed in the surface of said semiconductor substrate at its regions below respective parts of said tunneling oxide films so that said tunneling oxide films overlap partially with said impurity diffusion layers, respectively; and a pair of separating regions extending from longitudinal center lines of said two linear portions, respectively, perpendicular to the surface of said substrate, each of said separating regions being effective to electrically separate the floating gate of the memory cell formed in one of the element regions defined between said two linear portions from the floating gate of the memory cell formed in another element region adjacent to said one element region.

Claim 3

A nonvolatile semiconductor memory device as claimed in claim 1 wherein each of said tunneling oxide films has a thickness smaller than that of a center portion of said gate oxide film.

Claim 4

A nonvolatile semiconductor memory device as claimed in claim 1, wherein each of said tunneling oxide films has a thickness smaller than that of a center portion of said gate oxide film and each of said pair of impurity diffusion layers is separated from the center portion of said gate oxide film.

Claim 5

A nonvolatile semiconductor memory device as claimed in claim 1, wherein said floating gate is formed so as to overlap with each of said linear portions of said element-isolation structure.

Claim 6

A nonvolatile semiconductor memory device as claimed in claim 4, wherein said floating gate is overlapped with each of said pair of impurity diffusion regions at an overlapping area extending along said longitudinal direction, and said overlapping area has a width equal to, or shorter than 0.18 μm in a lateral direction.

Claim 7

A nonvolatile semiconductor memory device as claimed in claim 1, further comprising a control gate common to the memory cells located adjacent to each other in a lateral direction intersecting with said longitudinal direction; said control gate including a conductive layer electrically insulated from the floating gates and having a portion extending into each of said pair of separating regions.

Claim 8

A nonvolatile semiconductor memory device including a plurality of memory cells, each of said memory cells including a MOS type field-effect transistor having a floating gate, said memory device comprising: a semiconductor substrate; at least a pair of element-isolation films formed on a surface of said semiconductor substrate; an element region formed in a region between said pair of element-isolation films on the surface of said semiconductor substrate; each of said MOS transistors further including a gate oxide film formed in said element region on the surface of said semiconductor substrate and having two end portions closer to said element-isolation films, respectively, and a central portion therebetween, each of said end portions being formed with a tunneling oxide film having a thickness which is thinner than that of said central portion, and a pair of impurity diffusion layers constituting a source and a drain, respectively, wherein said floating gate is formed so as to cover said gate oxide film and overlap with each of said pair of element-isolation films, and said pair of impurity diffusion layers are formed in the surface of said semiconductor substrate at regions below said tunneling oxide films of the end portions of the gate oxide film, such that there exists a space between an area of the surface of said semiconductor substrate in which each of said impurity diffusion layers is formed and another area of the surface of said semiconductor substrate on which said central portion of said gate oxide film is formed; and an insulating film formed on said floating gate and having a portion extending substantially perpendicular to said surface of the substrate.

Claim 9

A nonvolatile semiconductor memory device including a plurality of memory cells, each of said memory cells including a MOS type field-effect transistor having a floating gate, said memory device comprising: a semiconductor substrate; at least a pair of element-isolation films formed on a surface of said semiconductor substrate; an element region formed in a region between said pair of element-isolation films on the surface of said semiconductor substrate; each of said MOS transistors further including a gate oxide film formed in said element region on the surface of said semiconductor substrate and having two end portions closer to said element-isolation films, respectively, and a central portion therebetween, each of said end portions being formed with a tunneling oxide film having a thickness which is thinner than that of said central portion, and a pair of impurity diffusion layers constituting a source and a drain, respectively, wherein said floating gate is formed so as to cover said gate oxide film and overlap with each of said pair of element-isolation films, and said pair of impurity diffusion layers are formed in the surface of said semiconductor substrate at regions below said tunneling oxide films of the end portions of the gate oxide film, such that there exists a space between an area of the surface of said semiconductor substrate in which each of said impurity diffusion layers is formed and another area of the surface of said semiconductor substrate on which said central portion of said gate oxide film is formed; and an insulating film formed on said floating gate and having a portion extending substantially perpendicular to said surface of the substrate.

Claim 10

A nonvolatile semiconductor memory device as claimed in claim 7, wherein each of said pair of impurity diffusion layers is separated from the central portion of said gate oxide film.

Claim 11

A nonvolatile semiconductor memory device as claimed in claim 7, wherein the floating gate is formed so as to overlap with each of said pair of impurity diffusion layers at an overlapping area extending along said longitudinal direction, and said overlapping area has a width equal to, or shorter than 0.18 μm in a lateral direction.

Claim 12

A nonvolatile semiconductor memory device as claimed in claim 7, further comprising a control gate common to the memory cells located adjacent to each other in a lateral direction intersecting with said longitudinal direction; said control gate including a conductive layer electrically insulated from said floating gate and having a portion extending into each of said pair of separating regions.