US5469383A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory cell array having continuous-strip field-oxide regions
Assignee: Texas Instruments Inc
•
Filing: 1994-06-24
•
Granted: 1995-11-21
•
Expires: 2014-06-24
Abstract
Abstract A CMOS memory cell array and a method of forming it, which avoids problems caused by field oxide corner-rounding. A moat pattern defines alternating columns of active areas and field oxide regions. A source line pattern defines rows of source lines. Silicon dopant is implanted in areas not covered by the source line pattern to form buried n+ source lines. The field oxide regions are formed in areas not covered by the moat pattern. Subsequent fabrication steps may be in accordance with conventional CMOS fabrication techniques.
Inventors
- 👤 Dave J. McElroy
- 👤 Manzur Gill
- 👤 Pradeep L. Shah
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 13:10
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B69/00
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
118 words
A memory cell array fabricated on a semiconductor substrate, each cell having a CMOS memory cell transistor, comprising: a silicon substrate; a thick field oxide region separating each column of memory cell transistors and defining active areas on which said transistors are fabricated, each of said thick field oxide regions forming a continuous strip; a source line associated with each row of memory cell transistors, and perpendicular to said field oxide regions, said source lines being implanted under said field oxide regions; and a number of memory cell transistors fabricated in said active areas, each memory cell having a gate, a drain, and a source, said sources being connected across rows of said transistors by said source lines.
Claim 2
Dependent Claim
118 words
A memory cell array fabricated on a semiconductor substrate, each cell having a CMOS memory cell transistor, comprising: a silicon substrate; a thick field oxide region separating each column of memory cell transistors and defining active areas on which said transistors are fabricated, each of said thick field oxide regions forming a continuous strip; a source line associated with each row of memory cell transistors, and perpendicular to said field oxide regions, said source lines being implanted under said field oxide regions; and a number of memory cell transistors fabricated in said active areas, each memory cell having a gate, a drain, and a source, said sources being connected across rows of said transistors by said source lines.
Claim 3
Dependent Claim
16 words
The memory cell array of claim 1, wherein said source lines are buried n-type source lines.
Claim 4
Dependent Claim
35 words
The memory cell array of claim 1, and further comprising a channel stop layer implanted under said thick field oxide regions, fabricated by means of a moat mask that blocks implantation in said active areas.
Claim 5
Dependent Claim
35 words
The memory cell array of claim 1, wherein said source lines are fabricated by means of implanting a dopant along source lines defined by a source line mask, before said field oxide regions are fabricated.
Claim 6
Dependent Claim
133 words
A CMOS memory array having rows and columns of memory cells, made by a buried source line process, comprising: a silicon substrate; a thick field oxide region separating each column of memory cells, made by growing said thick field oxide regions in continuous strips; a channel stop region implanted under each of said field oxide regions; a source line along each row of memory cells, perpendicular to said field oxide regions, said source lines being made by fabricating a source line mask and by implanting a silicon dopant along areas not covered by said source line mask; and a number of memory cell transistors fabricated in said active areas, each memory cell having a gate, a drain, and a source, said sources being connected across rows of said transistors by said source lines.
Claim 7
Dependent Claim
133 words
A CMOS memory array having rows and columns of memory cells, made by a buried source line process, comprising: a silicon substrate; a thick field oxide region separating each column of memory cells, made by growing said thick field oxide regions in continuous strips; a channel stop region implanted under each of said field oxide regions; a source line along each row of memory cells, perpendicular to said field oxide regions, said source lines being made by fabricating a source line mask and by implanting a silicon dopant along areas not covered by said source line mask; and a number of memory cell transistors fabricated in said active areas, each memory cell having a gate, a drain, and a source, said sources being connected across rows of said transistors by said source lines.
Claim 8
Dependent Claim
32 words
The memory cell array of claim 5, wherein said memory array is an electrically erasable and programmable memory and wherein said gate is a floating gate and further comprising a control gate.
Claim 9
Dependent Claim
20 words
The memory cell array of claim 5, wherein said thick field oxide regions are made by a localized oxidation process.
Claim 10
Dependent Claim
16 words
The memory cell array of claim 5, wherein said source lines are buried n-type source lines.
Claim 11
Dependent Claim
25 words
The memory cell array of claim 5, wherein said source line mask is made prior to said moat mask by means of a photoresist process.
Claim 12
Dependent Claim
29 words
The memory cell array of claim 9, wherein said source lines are formed by implanting and oxidizing a source line dopant prior to oxidizing said thick field oxide regions.
Claim 13
Dependent Claim
31 words
The memory cell array of claim 5, wherein said moat mask is fabricated before said source line mask, such that said source lines are implanted through portions of said moat mask.
Claim 14
Dependent Claim
30 words
The memory cell array of claim 5, wherein said channel stop regions are defined by means of a moat mask, which is removed prior to implantation of said source lines.
References Cited (Backward Citations)
US5323039A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-20 | 1999-05-22 | 1999-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-20 | 2003-05-22 | 2003-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-20 | 2007-05-22 | 2007-11-21 | $7700.00 | Window Closed / Lapsed |