Erasable programmable memory

Claim 2

An electrically-erasable, electrically-programmable read-only memory cell formed at a face of a semiconductor layer of a first conductivity type, comprising: a first doped region of a second conductivity type opposite that of said first conductivity type, formed at said face; a second doped region of said second conductivity type formed at said face and spaced from said first doped region by a channel region; a first insulator region overlying said first doped region; a thick insulator region overlying and abutting said semiconductor layer of said first conductivity type, said thick insulator region spaced from said channel region by said first insulator region, a relatively thin transition insulator region disposed between said first insulator region and said thick insulator region; a tunneling oxide window formed in said transition insulator region; a floating gate conductor formed insulatively overlying at least a portion of said channel region between said first and second doped regions, and adjoining said tunneling oxide window; and a control gate conductor insulatively overlying said floating gate conductor.

Claim 3

The memory cell of claim 1, wherein said first insulator region and said thick insulator region are formed of oxide.

Claim 4

The memory cell of claim 1, wherein said floating gate extends over said first insulator region.

Claim 5

The memory cell of claim 3, wherein said floating gate extends over at least a portion of said thick insulator region adjacent said first doped region.

Claim 6

The memory cell of claim 1, and further comprising a second insulator region overlying said second doped region.

Claim 7

The memory cell of claim 5, wherein said floating gate extends over at least a portion of said second insulator region.

Claim 8

The memory cell of claim 5 and further comprising a second thick insulator region adjacent said second doped region.

Claim 9

The memory cell of claim 7, wherein said floating gate extends over at least a portion of said second thick insulator region.

Claim 10

The memory cell of claim 7 wherein said second thick insulator region does not overlie said second doped region.

Claim 11

The memory cell of claim 1 and further comprising a channel stop region of said first conductivity type formed in said semiconductor layer beneath said thick insulator region.

Claim 12

The memory cell of claim I wherein said first doped region comprises a source region and said second doped region comprises a drain region.

Claim 13

An array of electrically-erasable, electrically-programmable read-only memory cells formed in columns and in rows at an angle to said columns, and at a face of semiconductor layer of a first conductivity type, comprising: for each column, an elongated drain region of a second conductivity type opposite said first conductivity type, forming a first bitline; for each column, an elongated source region of said second conductivity type, said source region forming a second bitline substantially in parallel to said first bitline and spaced therefrom by an elongated channel, a respective portion of said channel associated with each cell in the column, a length of said channel defined between said elongated source and drain regions; for each column, a first differentially grown insulator region overlying said elongated source region; for each column, a first thick insulator region adjacent said source region formed spaced from said channels in said column, by said first differentially grown insulator region, said thick insulator region isolating said column of cells from an adjacent column of cells; a thinner transition region formed between said differentially grown insulator region formed overlying said respective elongated source region and said thick insulator region formed adjacent said respective elongated source region; for each cell, a tunneling oxide window adjacent a portion of a respective elongated source region, and formed in a portion of said thinner transition region; for each cell, a floating gate insulatively adjacent at least a portion of said length of said channel between said source region and said drain region in the direction of said rows, and adjoining said tunneling oxide window; and for each row, a control gate insulatively overlying said floating gates in said row.

Claim 14

An array of electrically-erasable, electrically-programmable read-only memory cells formed in columns and in rows at an angle to said columns, and at a face of semiconductor layer of a first conductivity type, comprising: for each column, an elongated drain region of a second conductivity type opposite said first conductivity type, forming a first bitline; for each column, an elongated source region of said second conductivity type, said source region forming a second bitline substantially in parallel to said first bitline and spaced therefrom by an elongated channel, a respective portion of said channel associated with each cell in the column, a length of said channel defined between said elongated source and drain regions; for each column, a first differentially grown insulator region overlying said elongated source region; for each column, a first thick insulator region adjacent said source region formed spaced from said channels in said column, by said first differentially grown insulator region, said thick insulator region isolating said column of cells from an adjacent column of cells; a thinner transition region formed between said differentially grown insulator region formed overlying said respective elongated source region and said thick insulator region formed adjacent said respective elongated source region; for each cell, a tunneling oxide window adjacent a portion of a respective elongated source region, and formed in a portion of said thinner transition region; for each cell, a floating gate insulatively adjacent at least a portion of said length of said channel between said source region and said drain region in the direction of said rows, and adjoining said tunneling oxide window; and for each row, a control gate insulatively overlying said floating gates in said row.

Claim 15

The array of claim 12, wherein said floating gate extends over at least a portion of said differentially grown insulator region.

Claim 16

The array of claim 13, wherein each said floating gate extends over a respective portion of said thick insulator region formed adjacent said elongated source regions.

Claim 17

The array of claim 12, and further comprising, for each column, a differentially grown insulator region formed over said elongated drain region, floating gates in said column extending at least partly over said differentially grown insulator region.

Claim 18

The array of claim 12, and further comprising, for each column, a second thick insulator region formed adjacent said elongated drain region in said column and remote from said channels in said column, floating gates in said column extending at least partially over said second thick insulator region.

Claim 19

A non-volatile memory cell comprising: a semiconductor layer of a first conductivity type; a first doped region formed in said semiconductor layer, said first doped region of a second conductivity type opposite said first conductivity type; a second doped region formed in said semiconductor layer and spaced from said first doped region by a channel region, said second doped region of said second conductivity type; a first insulator region formed over said first doped region; a second insulator region formed over said second doped region; a third insulator region formed over a region of said semiconductor layer doped to said first conductivity type, said third insulator adjacent said first doped region; a tunnel region formed over said first doped region between said first and third insulator regions; a fourth insulator region formed over a region of said semiconductor layer of said first conductivity type, said fourth insulator adjacent said second doped region; a floating gate overlying said tunnel region, said first insulator region, said gate insulator, and said second insulator region and at least partially overlying said third and fourth insulator regions; and a control gate at least partially overlying said floating gate and insulated therefrom.

Claim 20

A non-volatile memory cell comprising: a semiconductor layer of a first conductivity type; a first doped region formed in said semiconductor layer, said first doped region of a second conductivity type opposite said first conductivity type; a second doped region formed in said semiconductor layer and spaced from said first doped region by a channel region, said second doped region of said second conductivity type; a first insulator region formed over said first doped region; a second insulator region formed over said second doped region; a third insulator region formed over a region of said semiconductor layer doped to said first conductivity type, said third insulator adjacent said first doped region; a tunnel region formed over said first doped region between said first and third insulator regions; a fourth insulator region formed over a region of said semiconductor layer of said first conductivity type, said fourth insulator adjacent said second doped region; a floating gate overlying said tunnel region, said first insulator region, said gate insulator, and said second insulator region and at least partially overlying said third and fourth insulator regions; and a control gate at least partially overlying said floating gate and insulated therefrom.

Claim 21

The cell of claim 17 wherein said first and second doped regions comprise n-doped silicon and said channel region comprises p-doped silicon.

Claim 22

The cell of claim 17 wherein said third insulator region is thicker than said first insulator region and said fourth insulator region is thicker than said second insulator region.

Claim 23

The cell of claim 17 wherein said first, second, third, and fourth insulator regions comprise oxide regions.

Claim 24

The cell of claim 17 wherein said control gate comprises polysilicon.

Claim 25

The cell of claim 17 wherein said floating gate comprises polysilicon.

Claim 26

The cell of claim 17 and further comprising channel stop regions formed in said semiconductor layer beneath said third and fourth insulator regions.