Manufacture of non-volatile memory element

Abstract

Abstract PURPOSE:To increase the junction breakdown strength at the junction part of an N type channel and a P type impurity diffused layer beneath a field part by a method wherein the concentration of the P type impurity beneath a control gate is thickened while that of a part near an N channel is thinned during the formation process of a P type impurity diffused layer as a channel stopper beneath an element isolating oxide film. CONSTITUTION:A gate oxide film 37 of EEPROM cell is formed in about 100Angstrom thick on a P type silicon substrate 31 by thermal oxidation process; a polysilicon 38 as a floating gate is formed on the oxide film 37 to be doped with phosphorus; and then a silicon nitride film 43 is formed on the polysilicon 38. A partial surface of the element isolating oxide film 37 is exposed so that B<+> may be implanted in the space between the polysilicons in the element isolating region formed of the oxide film 37 using the polysilicon 38 and the silicon nitride film 43 as masks and then P type diffused layers 39 in thick concentration are formed on the parts of P type impurity diffused layers 36 beneath the element isolation region 37. At this time, the film 43 works as a mask to avoid the boron ion implantation in the polysilicon 38. Finally, the silicon nitride film 43 is removed and an intermediate oxide insulating film 40 is formed.

Inventors

• 👤 Masami Ikegami
• 👤 池上　正美

Bibliographic Details