High density EEPROM cell array which can selectively erase each byte of data in each row of the array

Claim 1

An electrically-erasable programmable read only memory (EEPROM) comprising: an N-type semiconductor substrate; a plurality of P-type semiconductor wells formed in the N-type semiconductor substrate; a plurality of isolation field oxide regions formed in the substrate such that adjacent semiconductor wells are separated by an isolation field oxide region; a plurality of spaced-apart first oxide regions formed in each of the semiconductor wells such that each pair of adjacent first oxide regions defines a P-type active device region therebetween; a plurality of pairs of spaced-apart bit lines of N-type conductivity formed in each of the semiconductor wells such that each pair of bit lines is formed in a different P-type active device region, each bit line is formed adjacent to one first oxide region, and each pair of bit lines define a P-type channel region therebetween; a plurality of pairs of spaced-apart second oxide regions formed in each of the semiconductor wells such that each second oxide region is formed adjacent to one first oxide region, and such that each pair of second oxide regions overlies one pair of bit lines; and a plurality of memory cell structures formed in a plurality of rows on each of the semiconductor wells such that each memory cell structure in each row is formed over a different P-type channel region, and such that m memory cell structures are formed in each row, where m is an integer, wherein each memory cell structure includes: a layer of gate dielectric material having a tunnel opening, the layer of gate dielectric material adjoining the pair of second oxide regions, a layer of tunnel oxide formed in a portion of the tunnel opening, a layer of first conductive material formed over the layer of gate dielectric material and extending into the tunnel opening over the layer of tunnel oxide to form a floating gate, a layer of intermediate dielectric material formed over the layer of conductive material, and a layer of second conductive material formed over the layer of intermediate dielectric material to form a control gate.

Claim 16

A method for erasing memory cells in a selected row of cells of an electrically-erasable programmable read-only-memory (EEPROM), the selected row of cells including cells to be erased and cells to be maintained, the EEPROM including: an n-type semiconductor substrate; a plurality of p-type semiconductor wells formed in the n-type semiconductor substrate, the plurality of p-type wells including a p-type well that corresponds with the cells to be erased, and a p-type well that corresponds with the cells to be maintained; a plurality of isolation field oxide regions formed in the substrate such that adjacent semiconductor wells are separated by an isolation field oxide region; a plurality of spaced-apart first oxide regions formed in each of the semiconductor wells such that each pair of adjacent first oxide regions defines a p-type active device region therebetween; a plurality of pairs of spaced-apart bit lines of n-type conductivity formed in each of the semiconductor wells such that each pair of bit lines is formed in a different p-type active device region, each bit line being formed adjacent to one first oxide region, each pair of bit lines defining a p-type channel region therebetween; a plurality of pairs of spaced-apart second oxide regions formed in each of the semiconductor wells such that each second oxide region is formed adjacent to one first oxide region, and such that each pair of second oxide regions overlies one pair of bit lines; a plurality of memory cells formed in a plurality of rows on each of the semiconductor wells such that each memory cell in each row is formed over a different p-type channel region, and such that m memory cells are formed in each row, where m is an integer, the plurality of rows of memory cells including the selected row and an unselected row; and a plurality of word lines formed such that each word line connects each memory cell in one row of memory cells in each semiconductor well, the plurality of word lines including a word line that corresponds with the selected row, and a word line that corresponds with the unselected row, the method comprising the steps of: placing a first voltage on the word line that corresponds with the selected row; placing a second voltage on the word line that corresponds with the unselected row, the second voltage being greater than the first voltage; placing the second voltage on the plurality of pairs of bit lines; placing the second voltage on the p-well that corresponds with the memory cells to be erased; and placing the first voltage on the p-well to be maintained.

Claim 17

A method for erasing memory cells in a selected row of cells of an electrically-erasable programmable read-only-memory (EEPROM), the selected row of cells including cells to be erased and cells to be maintained, the EEPROM including: an n-type semiconductor substrate; a plurality of p-type semiconductor wells formed in the n-type semiconductor substrate, the plurality of p-type wells including a p-type well that corresponds with the cells to be erased, and a p-type well that corresponds with the cells to be maintained; a plurality of isolation field oxide regions formed in the substrate such that adjacent semiconductor wells are separated by an isolation field oxide region; a plurality of spaced-apart first oxide regions formed in each of the semiconductor wells such that each pair of adjacent first oxide regions defines a p-type active device region therebetween; a plurality of pairs of spaced-apart bit lines of n-type conductivity formed in each of the semiconductor wells such that each pair of bit lines is formed in a different p-type active device region, each bit line being formed adjacent to one first oxide region, each pair of bit lines defining a p-type channel region therebetween; a plurality of pairs of spaced-apart second oxide regions formed in each of the semiconductor wells such that each second oxide region is formed adjacent to one first oxide region, and such that each pair of second oxide regions overlies one pair of bit lines; a plurality of memory cells formed in a plurality of rows on each of the semiconductor wells such that each memory cell in each row is formed over a different p-type channel region, and such that m memory cells are formed in each row, where m is an integer, the plurality of rows of memory cells including the selected row and an unselected row; and a plurality of word lines formed such that each word line connects each memory cell in one row of memory cells in each semiconductor well, the plurality of word lines including a word line that corresponds with the selected row, and a word line that corresponds with the unselected row, the method comprising the steps of: placing a first voltage on the word line that corresponds with the selected row; placing a second voltage on the word line that corresponds with the unselected row, the second voltage being greater than the first voltage; placing the second voltage on the plurality of pairs of bit lines; placing the second voltage on the p-well that corresponds with the memory cells to be erased; and placing the first voltage on the p-well to be maintained.