US5786237A
Expired / Lapsed
US
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Method for forming a monolithic electronic module by stacking planar arrays of integrated circuit chips
Assignee: International Business Machines Corp
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Filing: 1995-08-16
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Granted: 1998-07-28
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Expires: 2015-08-16
Abstract
Abstract A fabrication method for manufacturing a monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.
Inventors
- 👤 Martha Ashley Clark Cockerill
- 👤 John George Maltabes
- 👤 Loretta Jean O'Connor
- 👤 Steven Howard Voldman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 01:19
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/23; H10W; H10W90/00; H10W72/00; H10W72/834; H10W90/20
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
160 words
A method for forming an electronic module comprising the steps of: (a) providing a plurality of planar arrays, each planar array of said plurality of planar arrays having a plurality of functional integrated circuit (IC) chips; (b) stacking said plurality of planar arrays to form an electronic module having at least one side surface; (c) polishing the at least one side surface of the electronic module to expose transfer metals extending thereto from at least some integrated circuit chips in each of said plurality of planar arrays, said polishing producing a polished side surface of the electronic module; and (d) depositing a two-dimensional metallization pattern on said polished side surface of the electronic module for at least partially electrically interconnecting the plurality of planar arrays, wherein said two-dimensional metallization pattern includes lateral interconnect for electrically interconnecting at least some integrated circuit chip in at least one planar array of said plurality of planar array stacked to form said electronic module.
Claim 2
Independent Claim
160 words
A method for forming an electronic module comprising the steps of: (a) providing a plurality of planar arrays, each planar array of said plurality of planar arrays having a plurality of functional integrated circuit (IC) chips; (b) stacking said plurality of planar arrays to form an electronic module having at least one side surface; (c) polishing the at least one side surface of the electronic module to expose transfer metals extending thereto from at least some integrated circuit chips in each of said plurality of planar arrays, said polishing producing a polished side surface of the electronic module; and (d) depositing a two-dimensional metallization pattern on said polished side surface of the electronic module for at least partially electrically interconnecting the plurality of planar arrays, wherein said two-dimensional metallization pattern includes lateral interconnect for electrically interconnecting at least some integrated circuit chip in at least one planar array of said plurality of planar array stacked to form said electronic module.
Claim 3
Dependent Claim
75 words
The method of claim 1, wherein each planar array has a first dimension and a second dimension, said second dimension being perpendicular to said first dimension, and wherein said providing step (a) further comprises supplying each planar array such that each planar array extends in said first dimension a length equal to at least one chip length and each planar array extends in said second dimension a length equal to at least two chip lengths.
Claim 4
Dependent Claim
70 words
The method of claim 2, wherein said method includes the step of separating the electronic module into at least two smaller electronic modules such that at least one of each planar array of said plurality of planar arrays extending in said first dimension at least one chip length and each planar array of said plurality of planar arrays extending in said second dimension at least two chip lengths is reduced.
Claim 5
Dependent Claim
52 words
The method of claim 1, wherein each planar array has an edge surface, and wherein said stacking step (b) includes the step of aligning said plurality of planar arrays such that said edge surfaces of said planar arrays at least partially define said at least one side surface of said electronic module.
Claim 6
Dependent Claim
47 words
The method of claim 1, wherein said stacking step (b) includes aligning said plurality of planar arrays comprising said pluralities of IC chips such that each IC chip of each planar array is aligned with an IC chip of an adjacent planar array in the electronic module.
Claim 7
Dependent Claim
76 words
The method of claim 5, wherein a first IC chip of a first planar array is columnarly aligned with a second IC chip from a second planar array in said electronic module, said first IC chip and said second IC chip forming an IC chip column, and wherein said step of depositing a metallization pattern comprises depositing a metallization pattern individually interconnecting said first IC chip and said second IC chip of said IC chip column.
Claim 8
Dependent Claim
26 words
The method of claim 1, wherein said providing step (a) includes dicing a wafer into at least two planar arrays of said plurality of planar arrays.
Claim 9
Dependent Claim
26 words
The method of claim 7, wherein said dicing step includes determining an optimal dicing pattern for maximizing a yield of said planar arrays from said wafer.
Claim 10
Dependent Claim
65 words
The method of claim 1, wherein said providing step (a) comprises providing a first planar array of said plurality of planar arrays having a first quantity of IC chips and providing a second planar array of said plurality of planar arrays having a second quantity of IC chips, and wherein said first quantity of IC chips and said second quantity of IC chips are different.
Claim 11
Independent Claim
187 words
A method for forming a planar array for use in an electronic module including a plurality of planar arrays, comprising the steps of: (a) providing a wafer having a plurality of integrated circuit (IC) chips; (b) dicing said wafer to form at least two planar arrays, each planar array of said at least two planar arrays comprising a plurality of functional IC chips; (c) stacking said plurality of planar arrays to form an electronic module having at least one side surface; (d) polishing the at least one side surface of the electronic module to expose transfer metals extending thereto from at least some integrated circuit chips in each of said plurality of planar arrays, said polishing producing a polished side surface of the electronic module; and (e) depositing a two-dimensional metallization pattern on said polished side surface of the electronic module for at least partially electrically interconnecting the plurality of planar arrays, wherein said two-dimensional metallization pattern includes lateral interconnect for electrically interconnecting at least some integrated circuit chips in at least one planar array of said plurality of planar arrays stacked to form said electronic module.
Claim 12
Independent Claim
187 words
A method for forming a planar array for use in an electronic module including a plurality of planar arrays, comprising the steps of: (a) providing a wafer having a plurality of integrated circuit (IC) chips; (b) dicing said wafer to form at least two planar arrays, each planar array of said at least two planar arrays comprising a plurality of functional IC chips; (c) stacking said plurality of planar arrays to form an electronic module having at least one side surface; (d) polishing the at least one side surface of the electronic module to expose transfer metals extending thereto from at least some integrated circuit chips in each of said plurality of planar arrays, said polishing producing a polished side surface of the electronic module; and (e) depositing a two-dimensional metallization pattern on said polished side surface of the electronic module for at least partially electrically interconnecting the plurality of planar arrays, wherein said two-dimensional metallization pattern includes lateral interconnect for electrically interconnecting at least some integrated circuit chips in at least one planar array of said plurality of planar arrays stacked to form said electronic module.
Claim 13
Dependent Claim
33 words
The method of claim 10, wherein prior to said dicing, said method includes the step of determining a dicing pattern, and wherein said dicing step (b) is performed according to said dicing pattern.
Claim 14
Dependent Claim
27 words
The method of claim 11, wherein said determining step includes optimizing said dicing pattern for providing a substantially maximized yield of said planar arrays from said wafer.
Claim 15
Dependent Claim
45 words
The method of claim 12, wherein prior to said determining step- said method includes testing each IC chip of said plurality of IC chips of said wafer to determine the functionality thereof, and wherein said determining step is at least partially based on said testing.
Claim 16
Dependent Claim
29 words
The method of claim 13, wherein said dicing step comprises employing a result of said testing step in dicing said wafer to form said at least two planar arrays.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-27 | 2002-01-26 | 2002-07-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-27 | 2006-01-26 | 2006-07-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-27 | 2010-01-26 | 2010-07-28 | $7700.00 | Window Closed / Lapsed |