Patent US5781031A successfully refreshed from Google Patents.
US5781031A
Expired / Lapsed
US
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Programmable logic array
Assignee: International Business Machines Corp
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Filing: 1995-11-21
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Granted: 1998-07-14
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Expires: 2015-11-21
Abstract
Abstract A programmable logic array (PLA) includes two direct-write EEPROM arrays, and PLA logic circuitry, such as feedback, drivers and input and output circuitry. One EEPROM array acts as an AND array and the other acts as n OR array. The PLA can be used for a memory function or a PLA function. In one aspect, the EEPROM arrays are placed on a first chip and the PLA logic circuitry a second chip. The first and second chips are stacked face-to-face, and force-responsive self-interlocking microconnectors are used to physically and electrically connect the separate chips. The separate chips are fabricated concurrently to reduce turn-around time.
Inventors
- 👤 Claude Louis Bertin
- 👤 John Edward Cronin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:29
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/1776; H03K19/17704; H03K19/1778; H03K19/17796; H10; H10W; H10W90/00; H10W46/00; H10W72/00; H10W72/01; H10W72/071; H10W72/072; H10W72/07231; H10W90/701; H10W90/721; H10W90/722; H10W90/724
Claims Analysis
Total Claims: 50
Claim 1
Independent Claim
192 words
A programmable logic array (PLA), comprising: a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA, wherein said plurality of memory cells and memory circuits comprises: a first memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, said first memory array acting as an AND array and said plurality of columns acting as product term lines; a second memory array coupled to said first memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, said second memory array acting as an OR array and said plurality of columns acting as product term lines; PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs; and mode selection circuitry permitting operation of said plurality of memory cells as a memory apart from said PLA.
Claim 2
Dependent Claim
192 words
A programmable logic array (PLA), comprising: a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA, wherein said plurality of memory cells and memory circuits comprises: a first memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, said first memory array acting as an AND array and said plurality of columns acting as product term lines; a second memory array coupled to said first memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, said second memory array acting as an OR array and said plurality of columns acting as product term lines; PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs; and mode selection circuitry permitting operation of said plurality of memory cells as a memory apart from said PLA.
Claim 3
Dependent Claim
13 words
The PLA of claim 1 wherein said plurality of outputs comprises output logic.
Claim 4
Dependent Claim
16 words
The PLA of claim 1 wherein said plurality of outputs comprise a plurality of output latches.
Claim 5
Dependent Claim
18 words
The PLA of claim 1, wherein said memory cells each comprise a logic circuit and a flip flop.
Claim 6
Dependent Claim
26 words
The PLA of claim 1, wherein each of said plurality of memory cells is independently addressable, thereby allowing operation thereof for storage apart from said PLA.
Claim 7
Dependent Claim
28 words
The PLA of claim 1 wherein each of said plurality of memory cells comprises a transistor, a flip-flop controlling gate bias on said transistor, and a non-volatile transistor.
Claim 8
Dependent Claim
26 words
The PLA of claim 6, wherein each of said plurality of memory cells further comprises an additional transistor coupled to said transistor for sensing said transistor.
Claim 9
Dependent Claim
29 words
The PLA of claim 6, wherein each of said plurality of memory cells further comprises an additional transistor coupled to said flip-flop for setting a state of said flip-flop.
Claim 10
Dependent Claim
98 words
A programmable logic array (PLA), comprising: a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA, and wherein said plurality of memory cells comprises a plurality of electrically erasable read only memory (EEPROM) cells; and PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs.
Claim 11
Dependent Claim
98 words
A programmable logic array (PLA), comprising: a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA, and wherein said plurality of memory cells comprises a plurality of electrically erasable read only memory (EEPROM) cells; and PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs.
Claim 12
Dependent Claim
18 words
The PLA of claim 9 wherein said plurality of EEPROM cells comprises a plurality of direct-write EEPROM cells.
Claim 13
Dependent Claim
93 words
A programmable logic array (PLA), comprising: a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA; and PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs, wherein said plurality of inputs comprises a plurality of bit partitioning input circuits.
Claim 14
Dependent Claim
93 words
A programmable logic array (PLA), comprising: a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA; and PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs, wherein said plurality of inputs comprises a plurality of bit partitioning input circuits.
Claim 15
Dependent Claim
91 words
A programmable logic array (PLA), comprising: a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA; PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs; and a plurality of drivers for driving said plurality of memory cells.
Claim 16
Dependent Claim
91 words
A programmable logic array (PLA), comprising: a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA; PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs; and a plurality of drivers for driving said plurality of memory cells.
Claim 17
Dependent Claim
100 words
A programmable logic array (PLA), comprising: a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA, wherein each of said plurality of memory cells comprises a transistor and a flip-flop controlling gate bias on said transistor; and PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs.
Claim 18
Dependent Claim
100 words
A programmable logic array (PLA), comprising: a plurality of memory cells and memory circuits, wherein said memory circuits allow operation of said memory cells for storage apart from said PLA, wherein each of said plurality of memory cells comprises a transistor and a flip-flop controlling gate bias on said transistor; and PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs.
Claim 19
Dependent Claim
26 words
The PLA of claim 13, wherein each of said plurality of memory cells further comprises an additional transistor coupled to said transistor for sensing said transistor.
Claim 20
Dependent Claim
29 words
The PLA of claim 13, wherein each of said plurality of memory cells further comprises an additional transistor coupled to said flip-flop for setting a state of said flip-flop.
Claim 21
Dependent Claim
113 words
A programmable logic array (PLA), comprising: a plurality of memory cells and memory circuits, wherein said plurality of memory cells reside on a first semiconductor chip; and PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs, and wherein said PLA logic circuitry resides on a second semiconductor chip stackable with said first semiconductor chip, said PLA further comprising a plurality of connectors for connecting said first semiconductor chip and said second semiconductor chip.
Claim 22
Dependent Claim
113 words
A programmable logic array (PLA), comprising: a plurality of memory cells and memory circuits, wherein said plurality of memory cells reside on a first semiconductor chip; and PLA logic circuitry coupled to at least some of said plurality of memory cells, said PLA logic circuitry comprising a plurality of inputs, a plurality of outputs, and a feedback connection between at least one of said plurality of outputs and at least one of said plurality of inputs, and wherein said PLA logic circuitry resides on a second semiconductor chip stackable with said first semiconductor chip, said PLA further comprising a plurality of connectors for connecting said first semiconductor chip and said second semiconductor chip.
Claim 23
Dependent Claim
30 words
The PLA of claim 16 wherein said plurality of connectors comprise a plurality of force-responsive self-interlocking microconnectors disposed on each of aid first semiconductor chip and said second semiconductor chip.
Claim 24
Dependent Claim
30 words
The PLA of claim 17 wherein said plurality of force-responsive self-interlocking microconnectors provide both a physical and an electrical connection between said first semiconductor chip and said second semiconductor chip.
Claim 25
Dependent Claim
71 words
The PLA of claim 17, wherein said plurality of connectors further comprise a plurality of repelling members disposed on one of said first semiconductor chip and said second semiconductor chip, said plurality of repelling members tending to push away a semiconductor chip coming into contact therewith, and said plurality of force-responsive self-interlocking microconnectors tending to pull said first semiconductor chip and said second semiconductor chip together, thereby providing a force-counter-force arrangement.
Claim 26
Dependent Claim
21 words
The PLA of claim 17, wherein said plurality of force-responsive self-interlocking microconnectors comprise a plurality of sizes providing differing alignment accuracy.
Claim 27
Dependent Claim
33 words
The PLA of claim 16, each of said first semiconductor chip and said second semiconductor chip further comprising at least one channel in which resides at least one of said plurality of connectors.
Claim 28
Dependent Claim
52 words
The PLA of claim 15, wherein said plurality of connectors comprise a plurality of metal bumps oppositely disposed on a facing surface of each said semiconductor chip, said PLA further comprising a means for connecting corresponding said oppositely disposed plurality of metal bumps, thereby providing both a physical and an electrical connection.
Claim 29
Dependent Claim
17 words
The PLA of claim 22, wherein said plurality of metal bumps comprise a plurality of gold bumps.
Claim 30
Dependent Claim
39 words
The PLA of claim 16 further comprising mode selection circuitry residing on one of said first semiconductor chip and said second semiconductor chip and permitting operation of said plurality of memory cells as a memory apart from said PLA.
Claim 31
Dependent Claim
13 words
The PLA of claim 16, wherein said plurality of outputs comprises output logic.
Claim 32
Dependent Claim
16 words
The PLA of claim 16, wherein said plurality of outputs comprises a plurality of output latches.
Claim 33
Dependent Claim
25 words
The PLA of claim 16 wherein each of said plurality of memory cells comprises a transistor and a flip-flop controlling gate bias on said transistor.
Claim 34
Dependent Claim
28 words
The PLA of claim 16 wherein each of said plurality of memory cells comprises a transistor, a flip-flop controlling gate bias on said transistor, and a non-volatile transistor.
Claim 35
Independent Claim
268 words
A method of making a programmable logic array (PLA), comprising: (a) providing a first memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, wherein said first memory array acts as an AND array, and wherein said plurality of columns act as product term lines; (b) providing a second memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, wherein said second memory array acts as an OR array, and wherein said plurality of columns act as product term lines; (c) programming said first memory array and said second memory array; (d) electrically coupling said plurality of columns of said first memory array with said plurality of columns of said second memory array; (e) providing PLA logic circuitry having a plurality of inputs and a plurality of outputs; (f) electrically coupling at least one of said plurality of outputs of said PLA logic circuitry with at least one of said plurality of inputs of said PLA logic circuitry, thereby providing at least one feedback connection; (g) electrically coupling at least some of said plurality of inputs of said first memory array with at least some of said plurality of inputs of said PLA logic circuitry; (h) electrically coupling at least some of said plurality of outputs of said second memory array with at least some of said plurality of outputs of said PLA logic circuitry; and (i) providing a plurality of memory circuits to allow operation of said first memory array and said second memory array for storage apart from said PLA.
Claim 36
Independent Claim
268 words
A method of making a programmable logic array (PLA), comprising: (a) providing a first memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, wherein said first memory array acts as an AND array, and wherein said plurality of columns act as product term lines; (b) providing a second memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, wherein said second memory array acts as an OR array, and wherein said plurality of columns act as product term lines; (c) programming said first memory array and said second memory array; (d) electrically coupling said plurality of columns of said first memory array with said plurality of columns of said second memory array; (e) providing PLA logic circuitry having a plurality of inputs and a plurality of outputs; (f) electrically coupling at least one of said plurality of outputs of said PLA logic circuitry with at least one of said plurality of inputs of said PLA logic circuitry, thereby providing at least one feedback connection; (g) electrically coupling at least some of said plurality of inputs of said first memory array with at least some of said plurality of inputs of said PLA logic circuitry; (h) electrically coupling at least some of said plurality of outputs of said second memory array with at least some of said plurality of outputs of said PLA logic circuitry; and (i) providing a plurality of memory circuits to allow operation of said first memory array and said second memory array for storage apart from said PLA.
Claim 37
Dependent Claim
45 words
The method of claim 29, wherein said first memory array comprises a first EEPROM memory array, wherein said second memory array comprises a second EEPROM memory array, and wherein said step (c) comprises programming said first EEPROM memory array and said second EEPROM memory array.
Claim 38
Dependent Claim
15 words
The method of claim 29 wherein said step (f) comprises electrically coupling through feedback circuitry.
Claim 39
Dependent Claim
21 words
The method of claim 29 wherein said steps (g) and (h) each comprise electrically coupling through a plurality of pass gates.
Claim 40
Dependent Claim
32 words
The method of claim 29, wherein each of said first memory array and said second memory array has independently addressable memory cells, thereby allowing operation thereof for storage apart from said PLA.
Claim 41
Independent Claim
299 words
A method of making a programmable logic array (PLA), comprising: (a) providing a first memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns; (b) providing a second memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, wherein said steps (a) and (b) comprise providing on a first semiconductor chip; (c) programming said first memory array and said second memory array; (d) electrically coupling said plurality of columns of said first memory array with said plurality of columns of said second memory array; (e) providing PLA logic circuitry having a plurality of inputs and a plurality of outputs, and wherein said step (e) comprises providing on a second semiconductor chip; (f) electrically coupling at least one of said plurality of outputs of said PLA logic circuitry with at least one of said plurality of inputs of said PLA logic circuitry, thereby providing at least one feedback connection; (g) electrically coupling at least some of said plurality of inputs of said first memory array with at least some of said plurality of inputs of said PLA logic circuitry; and (h) electrically coupling at least some of said plurality of outputs of said second memory array with at least some of said plurality of outputs of said PLA logic circuitry, said method further comprising steps of: forming a plurality of connectors for connecting said first semiconductor chip and said second semiconductor chip; and stacking said first semiconductor chip with said second semiconductor chip, wherein said first memory array acts as an AND array, wherein said plurality of columns act as product term lines, wherein said second memory array acts as an OR array, and wherein said plurality of columns act as product term lines.
Claim 42
Independent Claim
299 words
A method of making a programmable logic array (PLA), comprising: (a) providing a first memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns; (b) providing a second memory array having a plurality of inputs, a plurality of outputs and being arranged in rows and columns, wherein said steps (a) and (b) comprise providing on a first semiconductor chip; (c) programming said first memory array and said second memory array; (d) electrically coupling said plurality of columns of said first memory array with said plurality of columns of said second memory array; (e) providing PLA logic circuitry having a plurality of inputs and a plurality of outputs, and wherein said step (e) comprises providing on a second semiconductor chip; (f) electrically coupling at least one of said plurality of outputs of said PLA logic circuitry with at least one of said plurality of inputs of said PLA logic circuitry, thereby providing at least one feedback connection; (g) electrically coupling at least some of said plurality of inputs of said first memory array with at least some of said plurality of inputs of said PLA logic circuitry; and (h) electrically coupling at least some of said plurality of outputs of said second memory array with at least some of said plurality of outputs of said PLA logic circuitry, said method further comprising steps of: forming a plurality of connectors for connecting said first semiconductor chip and said second semiconductor chip; and stacking said first semiconductor chip with said second semiconductor chip, wherein said first memory array acts as an AND array, wherein said plurality of columns act as product term lines, wherein said second memory array acts as an OR array, and wherein said plurality of columns act as product term lines.
Claim 43
Dependent Claim
21 words
The method of claim 34 wherein said steps (a), (b), (c) and (d) are performed concurrently with steps (e) and (f).
Claim 44
Dependent Claim
31 words
The method of claim 34 wherein said step of forming comprises forming a plurality of force-responsive self-interlocking microconnectors disposed on each of said first semiconductor chip and said second semiconductor chip.
Claim 45
Dependent Claim
30 words
The method of claim 36 wherein said plurality of force-responsive self-interlocking microconnectors provide both a physical and an electrical connection between said first semiconductor chip and said second semiconductor chip.
Claim 46
Dependent Claim
30 words
The method of claim 36 wherein said step of stacking comprises pressing said first semiconductor-chip together with said second semiconductor chip such that said plurality of force-responsive self-interlocking microconnectors interlock.
Claim 47
Dependent Claim
41 words
The method of claim 36 further comprising a step of forming at least one channel on each of said first semiconductor chip and said second semiconductor chip on which to form at least one of said plurality of force-responsive self-interlocking microconnectors.
Claim 48
Dependent Claim
29 words
The method of claim 34 wherein said step of forming comprises forming a plurality of metal bumps oppositely disposed on said first semiconductor chip and said second semiconductor chip.
Claim 49
Dependent Claim
26 words
The method of claim 40 wherein said step of stacking comprises providing a means for physically and electrically connecting said plurality of oppositely disposed metal bumps.
Claim 50
Dependent Claim
55 words
The method of claim 34, wherein said PLA logic circuitry resides on a face of said second semiconductor chip, wherein said first memory array and said second memory array reside on a face of said first semiconductor chip and wherein said step of stacking comprises stacking said first semiconductor chip and said second semiconductor chip.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-07-13 | 2002-01-12 | 2002-07-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-13 | 2006-01-12 | 2006-07-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-13 | 2010-01-12 | 2010-07-14 | $7700.00 | Window Closed / Lapsed |