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US5778194A
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Method and apparatus for measuring performance of a computer bus
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1996-04-08
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Granted: 1998-07-07
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Expires: 2016-04-08
Abstract
Abstract A method and apparatus for a method for measuring performance of an I/O bus. The method includes the steps of (a) determining a number of I/O bus clock cycles that occur during I/O bus transactions involving a peripheral device during a time period, and (b) determining a bus performance value for the I/O bus based on the number of I/O bus clock cycles determined in step (a). One embodiment of the apparatus includes a mechanism for determining a bus utilization value for the I/O bus based on the number of I/O bus clock cycles counted by the counter. Another embodiment of the apparatus includes a mechanism for determining a bus efficiency value for the I/O bus based on the number of I/O bus clock cycles counted by the counter.
Inventors
- 👤 Craig C. McCombs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 02:44
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/3466; G06F11/349; G06F11/3409; G06F2201/00; G06F2201/87; G06F2201/88
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
95 words
A method of measuring performance of an I/O bus, comprising the steps of: (a) determining a number of I/O bus clock cycles that occur during I/O bus transactions involving a peripheral device during a time period, said determining step comprising the step of generating a first count value indicative of the number of I/O bus clock cycles that occur during I/O bus transactions involving the peripheral device during the time period; and (b) determining a bus performance value for the I/O bus based on the number of I/O bus clock cycles determined in step (a).
Claim 2
Independent Claim
95 words
A method of measuring performance of an I/O bus, comprising the steps of: (a) determining a number of I/O bus clock cycles that occur during I/O bus transactions involving a peripheral device during a time period, said determining step comprising the step of generating a first count value indicative of the number of I/O bus clock cycles that occur during I/O bus transactions involving the peripheral device during the time period; and (b) determining a bus performance value for the I/O bus based on the number of I/O bus clock cycles determined in step (a).
Claim 3
Dependent Claim
45 words
The method of claim 1, wherein step (b) includes the step of: (d) dividing the first count value by a second count value indicative of a total number of I/O bus clock cycles that occur during the time period to produce a bus utilization value.
Claim 4
Dependent Claim
45 words
The method of claim 1, wherein step (c) includes the steps of: (e) enabling a counter when a first I/O bus signal is asserted; and (f) disabling the counter when the first I/O bus signal is deasserted and a second I/O bus signal is deasserted.
Claim 5
Dependent Claim
14 words
The method of claim 3, wherein the I/O bus is a PCI Local Bus.
Claim 6
Dependent Claim
25 words
The method of claim 4, wherein the first I/O bus signal is a FRAME# signal, and the second I/O bus signal is an IRDY# signal.
Claim 7
Dependent Claim
32 words
The method of claim 1, further including the step of: (d) determining a number of I/O bus clock cycles that occur during data transfers involving the peripheral device during the time period.
Claim 8
Dependent Claim
40 words
The method of claim 6, wherein step (d) includes the step of: (e) generating a second count value indicative of the number of I/O bus clock cycles that occur during data transfers involving the peripheral device during the time period.
Claim 9
Dependent Claim
29 words
The method of claim 7, wherein step (b) includes the step of: (f) dividing the second count value by the first count value to produce a bus efficiency value.
Claim 10
Dependent Claim
61 words
The method of claim 7, wherein step (e) includes the steps of: (g) enabling a counter to count the number of I/O bus clock cycles that occur when a first I/O bus signal and a second I/O bus signal are asserted; and (h) disabling the counter when either the first I/O bus signal or the second I/O bus signal are deasserted.
Claim 11
Dependent Claim
14 words
The method of claim 9, wherein the I/O bus is a PCI Local Bus.
Claim 12
Dependent Claim
25 words
The method of claim 10, wherein the first I/O bus signal is an IRDY# signal, and the second I/O bus signal is a TRDY# signal.
Claim 13
Independent Claim
118 words
An apparatus for measuring performance of an I/O bus, comprising: a counter connected to the I/O bus for counting a number of I/O bus clock cycles that occur during I/O bus transactions involving a peripheral device during a time period; means for determining a bus utilization value for the I/O bus based on the number of I/O bus clock cycles counted by the counter; means for enabling the counter to count a number of I/O bus clock cycles that occur when a first I/O bus signal is asserted during the time period; and means for disabling the counter when the first I/O bus signal is deasserted and a second I/O bus signal is deasserted during the time period.
Claim 14
Independent Claim
118 words
An apparatus for measuring performance of an I/O bus, comprising: a counter connected to the I/O bus for counting a number of I/O bus clock cycles that occur during I/O bus transactions involving a peripheral device during a time period; means for determining a bus utilization value for the I/O bus based on the number of I/O bus clock cycles counted by the counter; means for enabling the counter to count a number of I/O bus clock cycles that occur when a first I/O bus signal is asserted during the time period; and means for disabling the counter when the first I/O bus signal is deasserted and a second I/O bus signal is deasserted during the time period.
Claim 15
Dependent Claim
33 words
The apparatus of claim 12, wherein: the I/O bus is a PCI Local Bus, the first I/O bus signal is a FRAME# signal, and the second I/O bus signal is an IRDY# signal.
Claim 16
Dependent Claim
76 words
The apparatus of claim 12, wherein: the counter stores a count value indicative of the number of I/O bus clock cycles that occur during I/O bus transactions involving a peripheral device during the time period, and the means for determining the bus utilization value includes means for dividing the count value by a value indicative of a total number of I/O bus clock cycles that occur during the time period to produce the bus utilization value.
Claim 17
Independent Claim
122 words
An apparatus for measuring performance of an I/O bus, comprising: a counter connected to the I/O bus for counting a number of I/O bus clock cycles that occur during data transfers involving the peripheral device during a time period; means for determining a bus efficiency value for the I/O bus based on the number of I/O bus clock cycles counted by the counter; means for enabling the counter to count a number of I/O bus clock cycles that occur when a first I/O bus signal and a second I/O bus signal are asserted during the time period; and means for disabling the counter when either the first I/O bus signal or the second I/O bus signal is deasserted during the time period.
Claim 18
Independent Claim
122 words
An apparatus for measuring performance of an I/O bus, comprising: a counter connected to the I/O bus for counting a number of I/O bus clock cycles that occur during data transfers involving the peripheral device during a time period; means for determining a bus efficiency value for the I/O bus based on the number of I/O bus clock cycles counted by the counter; means for enabling the counter to count a number of I/O bus clock cycles that occur when a first I/O bus signal and a second I/O bus signal are asserted during the time period; and means for disabling the counter when either the first I/O bus signal or the second I/O bus signal is deasserted during the time period.
Claim 19
Dependent Claim
33 words
The apparatus of claim 15, wherein: the I/O bus is a PCI Local Bus, the first I/O bus signal is an IRDY# signal, and the second I/O bus signal is a TRDY# signal.
Claim 20
Independent Claim
134 words
An apparatus for measuring performance of an I/O bus, comprising: a counter connected to the I/O bus for counting a number of I/O bus clock cycles that occur during data transfers involving the Peripheral device during a time period; and means for determining a bus efficiency value for the I/O bus based on the number of I/O bus clock cycles counted by the counter; wherein the counter stores a count value indicative of the number of I/O bus clock cycles that occur during data transfers involving the peripheral device during the time period, and the means for determining the bus efficiency value includes means for dividing the count value by a value indicative of a total number of I/O bus clock cycles that occur during the time period to produce the bus efficiency value.
Claim 21
Independent Claim
134 words
An apparatus for measuring performance of an I/O bus, comprising: a counter connected to the I/O bus for counting a number of I/O bus clock cycles that occur during data transfers involving the Peripheral device during a time period; and means for determining a bus efficiency value for the I/O bus based on the number of I/O bus clock cycles counted by the counter; wherein the counter stores a count value indicative of the number of I/O bus clock cycles that occur during data transfers involving the peripheral device during the time period, and the means for determining the bus efficiency value includes means for dividing the count value by a value indicative of a total number of I/O bus clock cycles that occur during the time period to produce the bus efficiency value.
References Cited (Backward Citations)
US4367525A
Cited
EP0076921A2
Cited
US4821178A
Cited
US5347647A
Cited
US5426741A
Cited
US5440751A
Cited
US5440722A
Cited
US5293384A
Cited
US5388237A
Cited
US5379384A
Cited
US5434872A
Cited
US5450551A
Cited
US5522050A
Cited
US5537664A
Cited
US5568621A
Cited
US5613075A
Cited
US5446869A
Cited
US5519872A
Cited
US5557757A
Cited
EP0671691A2
Cited
US5557755A
Cited
US5623645A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-06 | 2002-01-05 | 2002-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-06 | 2006-01-05 | 2006-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-06 | 2010-01-05 | 2010-07-07 | $7700.00 | Window Closed / Lapsed |