EP0671691A2
Expired / Lapsed
EP
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Storage controller and bus control method for use therewith
Assignee: Hitachi Ltd
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Filing: 1995-02-01
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Granted: —
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Expires: 2015-02-01
Abstract
Abstract A storage controller (2; 2a) comprising a storage device adapter (22; 522), a channel adapter (21a, 21b; 521a, 521b), a cache memory (24), a control memory (23), and a plurality of buses (26, 27; 56-58) connecting therebetween. The channel adapter communicates with a processor (1) and processes input/output requests issued by the processor. The storage device adapter controls a storage device (3) and data transfer between the storage device and the cache memory. The channel adapter and the storage device adapter exchanges control information via the control memory. The buses are used to transfer the data and the control information between the cache memory and the control memory, and the channel adapter and the storage device adapter. The controller also comprises bus load estimating means and bus mode selecting means. The bus load estimating means (201, 202) estimates bus load characteristics as an index based on the amount of data transfer during sequential access to the storage device. The bus mode selecting means (203) determines a bus mode of bus utilization based on the index. Each of the channel adapter and the storage device adapter has bus access means for accessing the buses in accordance with the bus mode selected by the bus mode selecting means.
Inventors
- 👤 Takao Satoh
- 👤 Hisaharu Takeuchi
- 👤 Yasuo Inoue
- 👤 Akira Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 15:17
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F11/00; G06F11/30; G06F11/34; G06F11/3466; G06F11/349; G06F11/3409; G06F2201/00; G06F2201/88; G06F2201/885
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
216 words
A storage controller (2; 2a) connected between a processor (1) and a storage device (3) for controlling data transfer therebetween, comprising: a storage device adapter (22; 522) for controlling said storage device; a cache memory (24) for storing part of the data held in said storage device; a channel adapter (21a, 21b; 521a, 521b) for communicating with said processor and for processing input/output requests received from said processor; a control memory (23) for storing control information used for communication between said storage device adapter and said channel adapter; a plurality of buses (26, 27; 56-58) each connected to at least two of said storage device adapters, said cache memory, said channel adapter and said control memory to transfer data and control information; bus load estimating means (201, 202) for obtaining an index for bus load characteristics indicating a proportion of data transfer and control information transfer on said plurality of buses; bus mode selecting means (203) for selecting one of a plurality of a bus mode that determines utilization of said buses based on the index obtained by said bus load estimating means; wherein each of said storage device adapter and said channel adapter has bus access means (204), for accessing said buses in accordance with the bus mode selected by said bus mode selecting means.
Claim 2
Dependent Claim
37 words
The storage controller according to claim 1, wherein said bus load estimating means (201, 202) includes means for estimating bus load characteristics based on an amount of data transfer during sequential access to said storage device (3).
Claim 3
Dependent Claim
40 words
The storage controller according to claim 1, wherein said bus mode selecting means (203) selects one of a sequential mode for emphasizing data transfer throughput and a random mode for emphasizing control information transfer throughput as said one bus mode.
Claim 4
Dependent Claim
55 words
The storage controller according to claim 3, wherein said bus load estimating means (201, 202) includes bus load measuring means for measuring and providing an actual bus load measurement on each of said buses and determination means for determining whether the bus loads are equally balanced among said buses on the basis of said measurement.
Claim 5
Dependent Claim
29 words
The storage controller according to claim 4, wherein said bus mode selecting means (203) makes a selection when said determination means has determined the bus loads are not balanced.
Claim 6
Dependent Claim
28 words
The storage controller according to claim 5, wherein said bus mode selecting means (203) selects a bus mode which reduces dispersion of the bus loads among said buses.
Claim 7
Dependent Claim
52 words
The storage controller according to claim 1, wherein said bus load estimating means includes sequential access residual byte detection means for detecting the residual bytes of sequential access of data transfer to said storage device (3), wherein said bus load estimating means adopts the residual bytes of sequential access as said index.
Claim 8
Dependent Claim
28 words
The storage controller according to claim 7, wherein said bus mode selecting means (203) selects the bus mode based on whether said residual bytes are increasing or decreasing.
Claim 9
Dependent Claim
62 words
The storage controller according to claim 1 comprising two buses (26, 27), wherein each of said buses is used for one of two uses consisting of control data transfer and data transfer, and wherein said bus mode selecting means (203) selects for each said bus a predetermined bus use assignment pattern made of the two bus uses as said one bus mode.
Claim 10
Dependent Claim
67 words
The storage controller according to claim 1 comprising three buses (56-58), wherein each of said buses is used for any one of three uses consisting of control data transfer, data transfer, and control data and data transfer, and wherein said bus mode selecting means (203) selects for each said bus a predetermined bus use assignment pattern made of the three bus uses as said one bus mode.
Claim 11
Dependent Claim
75 words
The storage controller according to claim 10, wherein said bus mode selecting means (203) in the event of a failure of one of said three buses, assigns one of the other two buses to control data transfer and the other of the two other buses to data transfer, and in the event of a failure of two of said three buses, assigns the remaining one of said three buses to control data and data transfer.
Claim 12
Dependent Claim
131 words
A bus control method for a storage controller (2; 2a) connected between a central processing unit (1) and a storage device (3) and comprising a plurality of modules and a plurality of buses transferring data and control information between the modules, said method comprising the steps of: obtaining, by one of the modules, bus load characteristics representing a proportion of data transfer and control information transfer on said plurality of buses; selecting, by said one module, one of a plurality of bus modes that determines bus utilization based on the bus load characteristics; communicating the selected bus mode selected in said selecting step from said one of the modules to the other of said modules; and accessing, by each of said modules, said buses in accordance with said selected bus mode.
Claim 13
Dependent Claim
38 words
The bus control method according to claim 11, wherein said selecting step includes a step of allocating at least one of data transfer and control information transfer to each of said buses according to said selected bus mode.
Claim 14
Dependent Claim
56 words
The bus control method according to claim 12, wherein said obtaining step includes the steps of measuring bus loads of said buses and detecting residual byte of sequential access of data transfer to said storage unit, and wherein said selecting step selects the one bus mode in accordance with said bus loads and said residual bytes.
Claim 15
Dependent Claim
45 words
The bus control method according to claim 13, further comprising a step of determining whether said bus loads of said buses are balanced among said buses, wherein said selecting step is executed when the bus loads are not balanced as a result of said determining.
Claim 16
Dependent Claim
124 words
A bus control method for controlling the utilization mode of buses connecting a plurality of modules constituting a storage controller (2; 2a), said bus control method comprising the steps of: determining whether an amount of data transfer controlled by input/output requests issued by a central processing unit to said storage controller is greater for sequential access transfer than random access transfer, and if so, switching to a bus utilization mode providing greater data transfer throughput than control data transfer throughput through said buses; and also determining whether said amount of data transfer is greater for random access transfer than sequential access transfer, and if so, switching to a bus utilization mode providing greater control data transfer throughput than data transfer throughput through said buses.
References Cited (Backward Citations)
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