Cached subtractive decode addressing on a computer bus

Claim 2

A subtractive decoding apparatus for connection to and communication with a bus in a computer system, the bus supporting transactions that can be both positively and subtractively decoded, the bus including lines providing a uniquely decoding address, and the bus including a device select line, said subtractive decoding apparatus comprising: subtractive decode circuitry for connection to the bus for providing a signal indicating when a current transaction on the bus is not positively decoded; a register with an input and an output, the input of said register driven by the lines of the bus, said register storing a first uniquely decoding address from the lines of the bus in response to said subtractive decode circuitry indicating that the current transaction on the bus is not positively decoded, and the output of said register providing the stored first uniquely decoding address; a comparator driven in response to the output of said register, said signal provided by said subtractive decode circuitry, and lines on the bus providing a uniquely decoding address, said comparator further providing a signal indicating a match between the first uniquely decoding address stored in said register and the second uniquely decoding address on the bus lines; and device select circuitry for asserting the device select line in response to either the signal from said subtractive decode circuitry indicating a transaction is not positively decoded or the signal from said comparator indicating a match between the first uniquely decoding address stored in said register and the second uniquely decoding address present on the bus.

Claim 3

The apparatus of claim 1, the computer system further including an expansion bus, wherein said subtractive decoding apparatus provides an interface between the bus and the expansion bus.

Claim 4

The apparatus of claim 1, the bus being a PCI bus and the computer system further including an EISA bus, wherein said subtractive decoding apparatus provides an interface between the PCI bus and the EISA bus.

Claim 5

The apparatus of claim 1, wherein the first and second uniquely decoding addresses include both a command type and an address.

Claim 6

A subtractive decoding apparatus for connection to and communication with a bus in a computer system, the bus supporting transactions that can be both positively and subtractively decoded, the bus including lines providing a uniquely decoding address, and the bus including a device select line, said subtractive decoding apparatus comprising: subtractive decode circuitry for connection to the bus providing a signal indicating when a current transaction on the bus is not positively decoded; an address cache with an input and an output, the input of said address cache driven by the lines of the bus, said address cache storing a plurality of uniquely decoding addresses from the lines of the bus in response to said subtractive decode circuitry indicating that the current transaction on the bus is not positively decoded, and the output of said address cache providing a signal indicating a match between any of the plurality of stored uniquely decoding addresses and the uniquely decoding addresses currently provided by the lines on the bus; and device select circuitry for asserting the device select line in response to either the signal from said subtractive decode circuitry indicating a transaction is not positively decoded or the signal on the output of said address cache indicating a match between any of the plurality of stored uniquely decoding addresses and the uniquely decoding addresses currently provided by the lines on the bus.

Claim 7

A subtractive decoding apparatus for connection to and communication with a bus in a computer system, the bus supporting transactions that can be both positively and subtractively decoded, the bus including lines providing a uniquely decoding address, and the bus including a device select line, said subtractive decoding apparatus comprising: subtractive decode circuitry for connection to the bus providing a signal indicating when a current transaction on the bus is not positively decoded; an address cache with an input and an output, the input of said address cache driven by the lines of the bus, said address cache storing a plurality of uniquely decoding addresses from the lines of the bus in response to said subtractive decode circuitry indicating that the current transaction on the bus is not positively decoded, and the output of said address cache providing a signal indicating a match between any of the plurality of stored uniquely decoding addresses and the uniquely decoding addresses currently provided by the lines on the bus; and device select circuitry for asserting the device select line in response to either the signal from said subtractive decode circuitry indicating a transaction is not positively decoded or the signal on the output of said address cache indicating a match between any of the plurality of stored uniquely decoding addresses and the uniquely decoding addresses currently provided by the lines on the bus.

Claim 8

The apparatus of claim 5, the computer system further including an expansion bus, wherein said subtractive decoding apparatus provides an interface between the bus and the expansion bus.

Claim 9

The apparatus of claim 5, the bus being a PCI bus and the computer system further including an EISA bus, wherein said subtractive decoding apparatus provides an interface between the PCI bus and the EISA bus.

Claim 10

The apparatus of claim 5, wherein the uniquely decoding addresses include both a command type and an address.

Claim 13

The method of claim 9, wherein said step (c) further comprises storing a plurality of uniquely decoding addresses present on the bus, and said step (e) further comprises comparing the current uniquely decoding address on the bus to the plurality of stored uniquely decoding addresses.

Claim 14

The method of claim 9, wherein said step (c) further comprises storing said uniquely decoding address in a register.

Claim 15

A computer system that provides improved subtractive decoding, said computer system comprising: a local bus that supports both positively and subtractively decoded transactions, said local bus including address lines; a processor coupled to said local bus; and a subtractive decode device connected to and communicating with said local bus, said subtractive decode device including: subtractive decode circuitry connected to said local bus providing a signal indicating when a current transaction on said local bus is not positively decoded; a register with an input and an output, the input of said register driven by the address lines of said local bus, said register storing a first uniquely decoding address from the address lines of said local bus in response to said subtractive decode circuitry indicating that the current transaction on said local bus is not positively decoded, and the output of said register providing the stored first uniquely decoding address; a comparator connected to the output of said register, said signal provided by said subtractive decode circuitry, and the address lines on said local bus providing a uniquely decoding address, for comparing a second uniquely decoding address on the address lines to the first uniquely decoding address stored in said register and provided as the output of said register, said comparator further providing a signal indicating a match between the first uniquely decoding address stored in said register and the second uniquely decoding address on said local bus; and device select circuitry for asserting the device select line in response to either the signal from said subtractive decode circuitry indicating a transaction is not positively decoded or the signal from said comparator indicating a match between the first uniquely decoding address stored in said register and the second uniquely decoding address present on said local bus.

Claim 16

A computer system that provides improved subtractive decoding, said computer system comprising: a local bus that supports both positively and subtractively decoded transactions, said local bus including address lines; a processor coupled to said local bus; and a subtractive decode device connected to and communicating with said local bus, said subtractive decode device including: subtractive decode circuitry connected to said local bus providing a signal indicating when a current transaction on said local bus is not positively decoded; a register with an input and an output, the input of said register driven by the address lines of said local bus, said register storing a first uniquely decoding address from the address lines of said local bus in response to said subtractive decode circuitry indicating that the current transaction on said local bus is not positively decoded, and the output of said register providing the stored first uniquely decoding address; a comparator connected to the output of said register, said signal provided by said subtractive decode circuitry, and the address lines on said local bus providing a uniquely decoding address, for comparing a second uniquely decoding address on the address lines to the first uniquely decoding address stored in said register and provided as the output of said register, said comparator further providing a signal indicating a match between the first uniquely decoding address stored in said register and the second uniquely decoding address on said local bus; and device select circuitry for asserting the device select line in response to either the signal from said subtractive decode circuitry indicating a transaction is not positively decoded or the signal from said comparator indicating a match between the first uniquely decoding address stored in said register and the second uniquely decoding address present on said local bus.

Claim 17

The computer system of claim 12 further comprising: an expansion bus; and said subtractive decode device converts transactions between said local bus and said expansion bus.

Claim 18

The computer system of claim 13, wherein said local bus is a PCI bus and said expansion bus is an EISA bus.