System for fast selection of non-cacheable address ranges using programmed array logic

Claim 1

A computer system capable of designating selected portions of memory as containing noncacheable data, comprising: a processor which generates memory addresses of 32 bit length referred to by A31 to A2 and memory controls; main memory; means for indicating if said main memory is to occupy the first 256 kbytes, 512 kbytes or 640 kbytes of the memory address space; means for indicating if said main memory contains a copy of selected data; a cache controller receiving memory addresses and memory controls from said processor and having an input for receiving a signal indicating whether a memory address contains noncacheable data; cache memory coupled to said cache controller; and an address decoder receiving said memory addresses and coupled to said main memory occupying means and main memory copy means comprising programmed array logic programmed to provide a signal to said cache controller noncacheable input to indicate the presence of noncacheable data if said memory address bits A31, A23, A22, A21, A20 and A19 are zero, said memory bit A18 is a one and said main memory is to occupy the first 256 kbytes; if said memory address bits A31, A23, A22, A21, A20 and A18 and A17 are zero, said memory address bit A19 is a one and said main memory is to occupy the first 512 kbytes; if said memory address bits A31, A23, A22, A21, A20 and A18 are zero and said memory address bits A19 and A17 are one; and if said memory address bits A31, A23, A22, A21, A20 and A17 are zero and said memory address bits A19 and A18 are one.