Method and apparatus for providing deterministic read access to main memory in a computer system

Claim 3

The method according to claim 1 wherein step (g) comprises the step of: reducing the bus arbitration priority of the host processor to a level lower than that of the retrying bus master.

Claim 4

The method according to claim 1 wherein step (f) comprises the steps of: relinquishing the local bus by the blocked bus master; and requiring all other non-processor bus masters coupled to the local bus not making any main memory access for the predetermined time period.

Claim 5

The method according to either claim 2 or 3 wherein step (h) comprises the step of: determining by the bridge circuit that the local bus is idle by monitoring at least one bus master-generated signal for a selected period.

Claim 6

The method according to claim 4 wherein the local bus comprises a peripheral component interconnect (PCI) bus.

Claim 7

A computer system comprising: a host central processing unit (CPU); a local bus; a main memory; a first bridge circuit coupling the host CPU to the main memory and to the local bus, the first bridge circuit including a write buffer; a first bus master coupled to the local bus, the first bus master arbitrating for access to the local bus to initiate and control operations on the local bus; a secondary bus; a second bridge circuit for transferring data therebetween the local and the secondary bus, the second bridge circuit including an arbitration circuit which controls access to the local bus in accordance with an arbitration algorithm; the first bridge circuit further including a controller which asserts a back-off signal when the bus master requests a read access to the main memory through the local bus and the write buffer is posted with write data from the host CPU, the bus master responding to the back-off signal by retrying the read access within a certain period that guarantees the retrying bus master access to the main memory over any other non-CPU bus masters coupled to either the local or the secondary bus, the controller and arbitration circuit operating to flush the data in the write buffer and keeping the write buffer disabled even after the flush to ensure the blocked bus master will not be blocked again because of posted write data in the write buffer when the blocked bus master retries the desired main memory access, the flushing operation causing the requesting priority of the host CPU to drop to a level lower than that of the retrying bus master in accordance with the arbitration algorithm to endure access to the local bus by the retrying bus master over the host CPU; and the bridge circuit further including signal monitoring means for detecting an idle condition on the local bus resulted from the bus master no longer making retry, the idle condition causing the write buffer to be reenabled for the host CPU.

Claim 8

A computer system comprising: a host central processing unit (CPU); a local bus; a main memory; a first bridge circuit coupling the host CPU to the main memory and to the local bus, the first bridge circuit including a write buffer; a first bus master coupled to the local bus, the first bus master arbitrating for access to the local bus to initiate and control operations on the local bus; a secondary bus; a second bridge circuit for transferring data therebetween the local and the secondary bus, the second bridge circuit including an arbitration circuit which controls access to the local bus in accordance with an arbitration algorithm; the first bridge circuit further including a controller which asserts a back-off signal when the bus master requests a read access to the main memory through the local bus and the write buffer is posted with write data from the host CPU, the bus master responding to the back-off signal by retrying the read access within a certain period that guarantees the retrying bus master access to the main memory over any other non-CPU bus masters coupled to either the local or the secondary bus, the controller and arbitration circuit operating to flush the data in the write buffer and keeping the write buffer disabled even after the flush to ensure the blocked bus master will not be blocked again because of posted write data in the write buffer when the blocked bus master retries the desired main memory access, the flushing operation causing the requesting priority of the host CPU to drop to a level lower than that of the retrying bus master in accordance with the arbitration algorithm to endure access to the local bus by the retrying bus master over the host CPU; and the bridge circuit further including signal monitoring means for detecting an idle condition on the local bus resulted from the bus master no longer making retry, the idle condition causing the write buffer to be reenabled for the host CPU.

Claim 9

The computer system of claim 6 wherein the signal monitoring means comprises first and second bus master generated signals, the idle condition resulting when the first and second bus master generated signals are deasserted for a selected time.

Claim 10

The computer system of claim 6 wherein the signal monitoring means comprises a bus master-generated signal and an arbitration circuit-generated signal, the idle condition resulting when the arbitration circuit-generated signal is detected without the assertion of the bus master-generated signal.

Claim 11

The computer system of either claim 7 or 8 wherein the arbitration algorithm comprises a round robin algorithm.

Claim 12

The computer system of claim 9 wherein the local bus comprises a peripheral component interface (PCI) bus.

Claim 13

The computer system of claim 10 wherein the secondary bus comprises either an industrial standard association (ISA) bus or an expanded industry standard association (EISA) bus.