US5168568A
Expired / Lapsed
US
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Delaying arbitration of bus access in digital computers
Assignee: Hewlett Packard Development Co LP
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Filing: 1989-02-06
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Granted: 1992-12-01
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Expires: 2009-02-06
Abstract
Abstract A bus arbitration protocol and accompanying bus arbitration logic for multiple-processor computer systems in which each processing module has a local cache. Several bus arbitration policies are enforced on contending devices which effectively introduce delay states into the arbitration behavior exhibited by each device. The bus arbitration protocol employs a distributed method of arbitration control involving an essentially fixed prioritization of arbitrating devices.
Inventors
- 👤 John S. Thayer
- 👤 Paul R. Culley
- 👤 Montgomery C. McGraw
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:40
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/368; G06F13/374
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
168 words
A computer system with bus arbitration, comprising: (a) a plurality of devices sharing a common bus, any one of said devices asserting a request signal on said bus after said any one requires control of the bus and wherein all of said devices which may require control of said bus have means for detecting said request signal; (b) arbitration circuitry coupled to said bus and detecting said request signal and asserting an arbitrate signal on said bus in response to said request signal; (c) only those of said devices requiring control of said bus asserting a priority signal in response to said arbitrate signal, and one of the devices asserting a highest level of priority gaining control of said bus; (d) said one of the devices including a timing circuit to prevent said one of the devices from reasserting said request signal for at least a first preselected time period after relinquishing control of said bus and after said one of the devices requires control of said bus.
Claim 2
Dependent Claim
168 words
A computer system with bus arbitration, comprising: (a) a plurality of devices sharing a common bus, any one of said devices asserting a request signal on said bus after said any one requires control of the bus and wherein all of said devices which may require control of said bus have means for detecting said request signal; (b) arbitration circuitry coupled to said bus and detecting said request signal and asserting an arbitrate signal on said bus in response to said request signal; (c) only those of said devices requiring control of said bus asserting a priority signal in response to said arbitrate signal, and one of the devices asserting a highest level of priority gaining control of said bus; (d) said one of the devices including a timing circuit to prevent said one of the devices from reasserting said request signal for at least a first preselected time period after relinquishing control of said bus and after said one of the devices requires control of said bus.
Claim 3
Dependent Claim
57 words
A system according to claim 1 including means in said one of the devices to prevent said one of the devices from relinquishing control of the bus for a second preselected time period after completing use of the bus unless during said second preselected time period said one of the devices detects said request signal being asserted.
Claim 4
Dependent Claim
16 words
A system according to claim 2 wherein said one of the devices is a processor device.
Claim 5
Dependent Claim
69 words
A system according to claim 1 wherein said one of the devices is a processor device, wherein said processor device includes means coupled to said arbitration circuitry for preventing said arbitration circuitry from asserting said arbitrate signal for a second preselected period of time after another of said devices asserts said request signal, unless said processor device completes use of said bus during said second preselected period of time.
Claim 6
Dependent Claim
63 words
A system according to claim 1, wherein said timing circuit further prevents said one of the devices from reasserting said request signal for said preselected time period after a first instant of time when said one of the devices does not detect said request signal after relinquishing control of said bus and after said one of the devices requires control of said bus.
Claim 7
Dependent Claim
16 words
A system according to claim 5, wherein said one of the devices is a processor device.
Claim 8
Dependent Claim
182 words
A multiprocessor system with bus arbitration, comprising: a) first and second processor devices and a plurality of other devices sharing a common bus, any one of said first and second devices and said other devices asserting a request signal on said bus after said any one requires control of said bus and wherein all of said devices which may require control of said bus have means to detect said request signal; b) arbitration circuitry coupled to said bus and detecting said request signal and asserting an arbitrate signal on said bus in response to said request signal; c) only those of said devices requiring control of said bus asserting a priority signal in response to said arbitrate signal, and one of the devices asserting a highest level of priority gaining control of said bus; d) said one of the devices including a timing circuit to prevent said one of the devices from reasserting said request signal for at least a first preselected time period after relinquishing control of said bus and after said one of the devices requires control of said bus.
Claim 9
Dependent Claim
182 words
A multiprocessor system with bus arbitration, comprising: a) first and second processor devices and a plurality of other devices sharing a common bus, any one of said first and second devices and said other devices asserting a request signal on said bus after said any one requires control of said bus and wherein all of said devices which may require control of said bus have means to detect said request signal; b) arbitration circuitry coupled to said bus and detecting said request signal and asserting an arbitrate signal on said bus in response to said request signal; c) only those of said devices requiring control of said bus asserting a priority signal in response to said arbitrate signal, and one of the devices asserting a highest level of priority gaining control of said bus; d) said one of the devices including a timing circuit to prevent said one of the devices from reasserting said request signal for at least a first preselected time period after relinquishing control of said bus and after said one of the devices requires control of said bus.
Claim 10
Dependent Claim
55 words
A system according to claim 7 including means in said one of the devices to prevent said one of the devices from relinquishing control of the bus for a second preselected time period after completing use of the bus unless during said second preselected time period said one of the devices detects said request signal.
Claim 11
Dependent Claim
17 words
A system according to claim 8 wherein said one of the devices is said first processor device.
Claim 12
Dependent Claim
61 words
A system according to claim 7 wherein said one of the devices includes means coupled to said arbitration circuitry for preventing said arbitration circuitry from asserting said arbitrate signal for a second preselected time period after another of said devices asserts said request signal, unless said one of the devices completes use of said bus during said second preselected time period.
Claim 13
Dependent Claim
17 words
A system according to claim 10, wherein said one of the devices is said first processor device.
Claim 14
Dependent Claim
63 words
A system according to claim 7, wherein said timing circuit further prevents said one of the devices from reasserting said request signal for said preselected time period after a first instant of time when said one of the devices does not detect said request signal after relinquishing control of said bus and after said one of the devices requires control of said bus.
Claim 15
Dependent Claim
38 words
A system according to claim 12, wherein said one of the devices is a processor device and one of said plurality of other devices has control of said bus after said processor device relinquishes control of said bus.
Claim 16
Independent Claim
229 words
A method for arbitrating for control of a common bus shard by a plurality of devices in a computer system, comprising the step of: a) providing a condition wherein a device requests control of said bus, wherein all of said devices wanting control of said bus can provide said condition; b) detecting said condition wherein said device requests control of said bus, and a condition wherein any device previously having control of said bus has relinquished control; c) when said conditions have been detected, asserting an arbitrate condition by signaling to all of said devices via said bus; d) detecting said arbitrate condition at all of said devices requesting control of said bus and asserting a priority code onto said bus by only those of said devices requesting control of said bus; e) withdrawing said priority code by all of said devices asserting a lower priority code to leave only a highest of the priority codes asserted, and the one of said devices asserting said highest of the priority codes assuming control of said bus; f) when said one of said devices as completed use of said bus, said one of said devices relinquishing control of said bus and refraining from providing said condition wherein said device requests control of said bus for at least a first preselected period of time after said device wants control of said bus.
Claim 17
Independent Claim
229 words
A method for arbitrating for control of a common bus shard by a plurality of devices in a computer system, comprising the step of: a) providing a condition wherein a device requests control of said bus, wherein all of said devices wanting control of said bus can provide said condition; b) detecting said condition wherein said device requests control of said bus, and a condition wherein any device previously having control of said bus has relinquished control; c) when said conditions have been detected, asserting an arbitrate condition by signaling to all of said devices via said bus; d) detecting said arbitrate condition at all of said devices requesting control of said bus and asserting a priority code onto said bus by only those of said devices requesting control of said bus; e) withdrawing said priority code by all of said devices asserting a lower priority code to leave only a highest of the priority codes asserted, and the one of said devices asserting said highest of the priority codes assuming control of said bus; f) when said one of said devices as completed use of said bus, said one of said devices relinquishing control of said bus and refraining from providing said condition wherein said device requests control of said bus for at least a first preselected period of time after said device wants control of said bus.
Claim 18
Dependent Claim
29 words
A method according to claim 14 wherein said devices include first and second processor devices, and wherein on of said processor devices asserts a higher priority than the other.
Claim 19
Dependent Claim
17 words
A method according to claim 14 wherein each one of said devices asserts a different priority code.
Claim 20
Dependent Claim
69 words
A method according to claim 14 wherein said one of the devices is a processor device, and said processor device retains control of said bus for a second preselected period of time after it has completed use of said bus, before said step of relinquishing control of said bus, unless during said second preselected period of time said condition wherein a device request access to said bus is detected.
Claim 21
Dependent Claim
37 words
A method according to claim 14 wherein said one of said devices having control of said bus prevents detection of said condition wherein another device request control of said bus for a second preselected period of time.
Claim 22
Dependent Claim
15 words
A method according to claim 18 wherein said first of said devices is a CPU.
Claim 23
Dependent Claim
79 words
A method according to claim 14, wherein when said one of the devices has completed use of said bus, relinquishing control of said bus and further refraining from providing said condition wherein said one of the devices request control of said bus for said preselected period of time after a first instant of time when said condition wherein any device requests control of said bus is not detected and said one of the devices wants control of said bus.
Claim 24
Dependent Claim
16 words
A method according to claim 20, wherein said one of the devices is a processor device.
Claim 25
Independent Claim
180 words
A method for arbitrating for control of a common bus shared by first and second CPU devices and a plurality of other devices in a computer system, comprising the steps of: a) detecting a condition wherein any one of said devices requests control of said bus; b) asserting an arbitrate condition in response to detecting said request condition by signaling to all of said devices via said bus; c) detecting said arbitrate condition at all of said devices requesting control of said bus and asserting a priority code onto said bus only those of said devices requesting control of said bus to determine which one of said devices is asserting a highest of the priority codes and allowing said one of the devices to assume control of said bus; d) when said one of the devices has completed use of said bus, said one of the devices relinquishing control of said bus and refraining from requesting control of said bus for at least a first preselected period of time after said one of the devices wants control of said bus.
Claim 26
Independent Claim
180 words
A method for arbitrating for control of a common bus shared by first and second CPU devices and a plurality of other devices in a computer system, comprising the steps of: a) detecting a condition wherein any one of said devices requests control of said bus; b) asserting an arbitrate condition in response to detecting said request condition by signaling to all of said devices via said bus; c) detecting said arbitrate condition at all of said devices requesting control of said bus and asserting a priority code onto said bus only those of said devices requesting control of said bus to determine which one of said devices is asserting a highest of the priority codes and allowing said one of the devices to assume control of said bus; d) when said one of the devices has completed use of said bus, said one of the devices relinquishing control of said bus and refraining from requesting control of said bus for at least a first preselected period of time after said one of the devices wants control of said bus.
Claim 27
Dependent Claim
29 words
A method according to claim 22 wherein said devices include first and second processor devices, and wherein one of said processor devices asserts a higher priority than the other.
Claim 28
Dependent Claim
17 words
A method according to claim 22 wherein each one of said devices asserts a different priority code.
Claim 29
Dependent Claim
69 words
A method according to claim 22 wherein said one of the devices is a processor device, and said processor device retains control of said bus for a second preselected period of time after it has completed use of said bus, before said step of relinquishing control of said bus, unless during said second preselected period of time said condition wherein a device requests control of said bus is detected.
Claim 30
Dependent Claim
57 words
A method according to claim 22 wherein an arbitration condition is asserted upon detecting said condition wherein a device requests control of said bus, and wherein a first of said devices while having control of said bus prevents detection of said condition wherein a device requests control of said bus for a second preselected period of time.
Claim 31
Dependent Claim
60 words
A method according to claim 22, wherein said one of the devices has completed use of said bus, relinquishing control of said bus for said preselected period of time after a first instant of time when said condition wherein any device requests control of said bus is not detected and said one of the devices wants control of said bus.
Claim 32
Dependent Claim
29 words
A method according to claim 27, wherein said one of the devices is a CPU device and one of said plurality of other devices has control of said bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-01 | 1996-06-01 | 1996-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-01 | 2000-06-01 | 2000-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-01 | 2004-06-01 | 2004-12-01 | $7700.00 | Window Closed / Lapsed |