Patent US1728591A successfully refreshed from Google Patents.
US5440751A
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US
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Burst data transfer to single cycle data transfer conversion and strobe signal conversion
Assignee: Hewlett Packard Development Co LP
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Filing: 1991-06-21
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Granted: 1995-08-08
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Expires: 2011-06-21
Abstract
Abstract An apparatus which converts burst mode bus cycles into single cycle mode cycles and converts separate address and data strobe signals into a single address strobe in a computer system. The apparatus also receives an address strobe signal, a number of address signals and the length of the burst when a device begins a burst cycle. After the first cycle of the burst transfer is complete, the apparatus initiates each subsequent cycle comprising the burst transfer by incrementing the address signals and providing additional address strobe signals until the burst is complete. The logic also facilitates address pipelining by monitoring a next address signal generated by the device. The apparatus monitors the separate address strobe and data strobe signals and generates the single address strobe signal on the next clock cycle after the address and data strobe signals are asserted. If only the address strobe signal is asserted at the beginning of a cycle, then the single address strobe signal is asserted only after valid data is available on the bus and the data strobe signal is asserted. The apparatus also monitors next address signals generated by the device to facilitate pipelining.
Inventors
- 👤 Paul Santeler
- 👤 Gary W. Thome
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 13:10
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0877; G06F12/0879
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
430 words
An apparatus for converting burst mode transfers into single cycle mode transfers in a computer system, the apparatus comprising: a system bus; a first device connected to said system bus and executing burst transfers on said system bus, wherein the first device generates a first address strobe signal and a plurality of address signals at the beginning of said burst transfer and no address strobe signals thereafter during the burst transfer, wherein a first number of said plurality of address signals are provided to said system bus, and wherein the first device generates signals indicative of said burst transfer size at the beginning of said burst transfer; a second device having a first number and a second number of address signal inputs and being connected to said system bus and only capable of receiving single cycle mode transfers with an address strobe for each transfer, wherein said first number of said plurality of address signal inputs are connected to said first number of said address signals on said system bus provided by said first device and said second number of said address signal inputs are connected to said system bus and wherein said first number is greater than said second number; means coupled to said system bus and to said first device for receiving a second number of address signals from said first device and for receiving said first address strobe signal from said first device and storing said second number of address signals; means coupled to said second number of address signal storing means for incrementing said second number of address signals, wherein said incrementing means increments said second number of address signals for each cycle comprising said burst transfer after the first transfer; means coupled to said second device for providing an additional address strobe signal to said second device for each cycle comprising said burst transfer except the first transfer; means coupled to the system bus, said additional address strobe means and said address signal incrementing means for providing said incremented second number of address signals to the system bus approximately contemporaneously with providing said additional address strobe signal, wherein said second number of address signals are provided to said system bus to correspond to said second number of address signal inputs of said second device; and means coupled to the first device and said additional address strobe means for terminating providing of additional address strobes when the number of additional address strobes provided indicates that, based on size of the burst transfer as indicated by the first device, the last additional address strobe has been provided.
Claim 2
Independent Claim
430 words
An apparatus for converting burst mode transfers into single cycle mode transfers in a computer system, the apparatus comprising: a system bus; a first device connected to said system bus and executing burst transfers on said system bus, wherein the first device generates a first address strobe signal and a plurality of address signals at the beginning of said burst transfer and no address strobe signals thereafter during the burst transfer, wherein a first number of said plurality of address signals are provided to said system bus, and wherein the first device generates signals indicative of said burst transfer size at the beginning of said burst transfer; a second device having a first number and a second number of address signal inputs and being connected to said system bus and only capable of receiving single cycle mode transfers with an address strobe for each transfer, wherein said first number of said plurality of address signal inputs are connected to said first number of said address signals on said system bus provided by said first device and said second number of said address signal inputs are connected to said system bus and wherein said first number is greater than said second number; means coupled to said system bus and to said first device for receiving a second number of address signals from said first device and for receiving said first address strobe signal from said first device and storing said second number of address signals; means coupled to said second number of address signal storing means for incrementing said second number of address signals, wherein said incrementing means increments said second number of address signals for each cycle comprising said burst transfer after the first transfer; means coupled to said second device for providing an additional address strobe signal to said second device for each cycle comprising said burst transfer except the first transfer; means coupled to the system bus, said additional address strobe means and said address signal incrementing means for providing said incremented second number of address signals to the system bus approximately contemporaneously with providing said additional address strobe signal, wherein said second number of address signals are provided to said system bus to correspond to said second number of address signal inputs of said second device; and means coupled to the first device and said additional address strobe means for terminating providing of additional address strobes when the number of additional address strobes provided indicates that, based on size of the burst transfer as indicated by the first device, the last additional address strobe has been provided.
Claim 3
Dependent Claim
56 words
The apparatus of claim 1, wherein said second device provides a complete signal for each cycle comprising said burst transfer to said system bus indicating that a subsequent cycle may begin, and wherein said additional address strobe signal providing means receives said complete signal and provides said additional address strobe signal after receiving said complete signal.
Claim 4
Dependent Claim
15 words
The apparatus of claim 2, wherein said complete signal is a next address request signal.
Claim 5
Dependent Claim
48 words
The apparatus of claim 1, wherein said first device includes means for providing further address strobe signals upon receipt of a cycle complete signal and wherein said terminating means includes means for providing the cycle complete signal to the first device after terminating providing of additional address strobes.
References Cited (Backward Citations)
US4920540A
Cited
US5179663A
Cited
US5083260A
Cited
US5134699A
Cited
US5146582A
Cited
US5101492A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-07 | 1999-02-06 | 1999-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-07 | 2003-02-06 | 2003-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-07 | 2007-02-06 | 2007-08-08 | $7700.00 | Window Closed / Lapsed |