Bonding pad for a semiconductor chip

Claim 2

A bonding pad for a semiconductor device having active regions interconnected by a metal pattern, the bonding pad comprising: a metal region disposed over the metal pattern, the metal region defining a bonding pad area over the active regions, the metal region being in direct contact with the metal pattern for substantially the whole bonding pad area, a thickness of the metal region preventing perforation of the metal region by a bonding wire during a bonding process of bonding the bonding wire to the metal region so that a mechanical stress caused by the bonding wire during the bonding process is substantially entirely sustained by the metal region; and a passivating material layer disposed between the metal pattern and the metal region except for under said bonding pad area defined by the metal region.

Claim 3

The bonding pad according to claim 1, wherein said bonding pad area includes islands of passivating material provided between the metal pattern and the metal region to cause the metal region to have a rough surface, the islands of passivating material each having an area substantially smaller than the bonding pad area so that the metal region is in direct contact with the metal pattern for substantially the whole bonding pad area.

Claim 4

The bonding pad according to claim 1 wherein at least one of the metal region and the metal pattern is composed of an alloy of aluminum, silicon and titanium.

Claim 5

The bonding pad according to claim 1 wherein at least one of the metal region and the metal pattern is composed of an alloy of aluminum, silicon and copper.

Claim 6

The bonding pad according to claim 1 wherein the thickness of the metal region is greater than a thickness of the metal pattern.

Claim 7

A bonding pad for a semiconductor device having active regions interconnected by a metal pattern, the bonding pad comprising: a metal region disposed over the metal pattern, the metal region defining a bonding pad area over the active regions, the metal region being in direct contact with the metal pattern for substantially the whole bonding pad area, a thickness of the metal region preventing perforation of the metal region by a bonding wire during a bonding process of bonding the bonding wire to the metal region so that a mechanical stress caused by the bonding wire during the bonding process is substantially entirely sustained by the metal region; and a passivating material layer, comprising a dielectric, disposed between the metal pattern and the metal region except for under said bonding pad area defined by the metal region; whereby the passivating material layer operates both to separate the metal pattern from the metal region, except for under the bonding pad area, and to protect a surface of the semiconductor device.

Claim 8

A bonding pad for a semiconductor device having active regions interconnected by a metal pattern, the bonding pad comprising: a metal region disposed over the metal pattern, the metal region defining a bonding pad area over the active regions, the metal region being in direct contact with the metal pattern for substantially the whole bonding pad area, a thickness of the metal region preventing perforation of the metal region by a bonding wire during a bonding process of bonding the bonding wire to the metal region so that a mechanical stress caused by the bonding wire during the bonding process is substantially entirely sustained by the metal region; and a passivating material layer, comprising a dielectric, disposed between the metal pattern and the metal region except for under said bonding pad area defined by the metal region; whereby the passivating material layer operates both to separate the metal pattern from the metal region, except for under the bonding pad area, and to protect a surface of the semiconductor device.