US5768288A — Method and apparatus for programming a programmab…

Claim 1

Independent Claim 170 words

A test circuit in a logic device having a memory location, said test circuit comprising: a serial input port; an address storage element coupled to said serial input port, said address storage element receiving address information corresponding to said memory location from said serial input port; a data storage element coupled to said serial input port, said data storage element receiving program data from said serial input port; control logic coupled to said address storage element and said data storage element, said control logic controlling when said program data is programmed into said memory location addressed by said address information; and verify logic coupled to said data storage element and said memory location and receiving verify data read from said memory location, said control logic controlling when said verify data is read from said memory location, said verify logic generating an output signal in response to comparing said verify data and said program data, wherein said verify logic uses said program data as a mask in generating said output signal.

Claim 2

Dependent Claim 170 words

A test circuit in a logic device having a memory location, said test circuit comprising: a serial input port; an address storage element coupled to said serial input port, said address storage element receiving address information corresponding to said memory location from said serial input port; a data storage element coupled to said serial input port, said data storage element receiving program data from said serial input port; control logic coupled to said address storage element and said data storage element, said control logic controlling when said program data is programmed into said memory location addressed by said address information; and verify logic coupled to said data storage element and said memory location and receiving verify data read from said memory location, said control logic controlling when said verify data is read from said memory location, said verify logic generating an output signal in response to comparing said verify data and said program data, wherein said verify logic uses said program data as a mask in generating said output signal.

Claim 3

Dependent Claim 24 words

The test circuit of claim 1, wherein said output signal generated by said verify logic indicates that said program data matches said verify data.

Claim 4

Dependent Claim 26 words

The test circuit of claim 2, wherein said program data matches said verify data when said program data and said verify data comprise equivalent logic states.

Claim 5

Dependent Claim 26 words

The test circuit of claim 2, wherein said program data matches said verify data when said program data and said verify data comprise different logic states.

Claim 6

Dependent Claim 17 words

The test circuit of claim 1, further comprising a serial output port coupled to said verify logic.

Claim 7

Dependent Claim 15 words

The test circuit of claim 1, wherein said program data comprises one program data bit.

Claim 8

Dependent Claim 17 words

The test circuit of claim 1, wherein said program data comprises a plurality of program data bits.

Claim 9

Dependent Claim 62 words

The test circuit of claim 1, wherein said verify logic comprises: a verify register coupled to said control logic and said serial input port; and compare logic coupled to said memory location and said data storage element, wherein said compare logic compares said program data with said verify data and uses said program data as a mask in generating a verify signal.

Claim 10

Dependent Claim 15 words

The test circuit of claim 8, wherein said verify register comprises a one bit register.

Claim 11

Dependent Claim 84 words

The test circuit of claim 8, wherein said compare logic comprises: a first logic block coupled to said data storage element and operative to receive said verify data read from said memory location, said first logic block generating a plurality of mask result signals in response to the comparison of said program data and said verify data; and a second logic block coupled to said first logic block, said second logic block receiving said plurality of mask result signals and generating said verify signal.

Claim 12

Dependent Claim 16 words

The test circuit of claim 10, wherein said verify signal is coupled to said verify register.

Claim 13

Dependent Claim 37 words

The test circuit of claim 11 wherein said verify register is coupled to a clock signal and said verify register provides said verify signal as said output signal in response to a transition of said clock signal.

Claim 14

Dependent Claim 14 words

The test circuit of claim 10, wherein said output signal comprises said verify signal.

Claim 15

Dependent Claim 101 words

The test circuit of claim 10, wherein: said first logic block comprises a first plurality of logic elements coupled to a second plurality of logic elements, said first plurality of logic elements generating a plurality of match signals in response to a comparison of said program data with said verify data, said second plurality of logic elements generating said plurality of mask result signals in response to a comparison of said plurality of match signals with said program data; and said second logic block comprises a verify logic element receiving said plurality of mask result signals and generating said verify signal.

Claim 16

Dependent Claim 44 words

The test circuit of claim 14, wherein: each of said first plurality of logic elements provides an exclusive OR (XOR) function; each of said second plurality of logic elements provides an AND function; and said verify logic element provides an inverted OR (NOR) function.

Claim 17

Dependent Claim 66 words

The test circuit of claim 10, wherein: said first logic block comprises a first plurality of logic elements, said first plurality of logic elements generating said plurality of mask result signals in response to a comparison of said program data with said verify data; and said second logic block comprises a verify logic element receiving said plurality of mask result signals and generating said verify signal.

Claim 18

Dependent Claim 30 words

The test circuit of claim 16, wherein: each of said first plurality of logic elements provides an AND function and said verify logic element provides an inverted OR (NOR) function.

Claim 19

Dependent Claim 32 words

The test circuit of claim 16, wherein: each of said first plurality of logic elements provides an inverted OR (NOR) function; and said verify logic element provides an inverted OR (NOR) function.

Claim 20

Dependent Claim 55 words

The test circuit of claim 1, wherein the data storage element stores a first number of program data bits, and said verify data read from said memory location comprises a second number of verify data bits, wherein said second number of verify data bits is not equal to said first number of program data bits.

Claim 21

Dependent Claim 74 words

The test circuit of claim 19, wherein said first number of program data bits is greater than said second number of verify data bits by a first amount of program data bits, and wherein each of said first amount of program data bits comprises a logic state such that said verify logic generates said output signal based on comparing said first number of program data bits with said second number of verify data bits.

Claim 22

Dependent Claim 13 words

The test circuit of claim 1, wherein said test circuit supports single-bit programming.

Claim 23

Dependent Claim 12 words

A programmable logic device having the test circuit as in claim 1.

Claim 24

Dependent Claim 27 words

A test system having the test circuit of claim 1, and further comprising: another test circuit, wherein said test circuit is cascaded with said another test circuit.

Claim 25

Dependent Claim 42 words

The test system of claim 23, wherein: said test circuit further comprises a serial output port coupled to said verify logic; and said another test circuit comprises another serial input port, said another serial input port coupled to said serial output port.

Claim 26

Dependent Claim 23 words

The test system of claim 24, wherein said another test circuit further comprises another verify logic coupled to said another serial input port.

Claim 27

Dependent Claim 100 words

The test circuit of claim 1, further comprising: a test mode select input port coupled to said control logic, said test circuit receiving a test mode select signal from said test mode select input port; a clock input port coupled to said address storage element, said data storage element, said control logic and said verify logic, said test circuit receiving a clock input signal from said clock input port; and an instruction storage element coupled to said serial input port, said clock input port and said control logic, said instruction storage element receiving instruction information from said serial input port.

Claim 28

Dependent Claim 40 words

The test circuit of claim 26, further comprising: a bypass register element coupled to said serial input port and said clock input port and/or a boundary scan register element coupled to said serial input port and said clock input port.

Claim 29

Dependent Claim 162 words

A test circuit in a programmable logic device having a memory location, said test circuit comprising: a serial input port; an address storage element coupled to said serial input port, said address storage element receiving address information corresponding to said memory location from said serial input port; a data storage element coupled to said serial input port, said data storage element receiving program data from said serial input port; control logic coupled to said address storage element and said data storage element, said control logic controlling when said program data is programmed into said memory location addressed by said address information; and verify logic comprising a verify register coupled to compare logic, said verify register coupled to said control logic and said serial input port, said compare logic coupled to said memory location and said data storage element, wherein said control logic controls when verify data is read from said memory location and compared with said program data by said compare logic.

Claim 30

Dependent Claim 162 words

A test circuit in a programmable logic device having a memory location, said test circuit comprising: a serial input port; an address storage element coupled to said serial input port, said address storage element receiving address information corresponding to said memory location from said serial input port; a data storage element coupled to said serial input port, said data storage element receiving program data from said serial input port; control logic coupled to said address storage element and said data storage element, said control logic controlling when said program data is programmed into said memory location addressed by said address information; and verify logic comprising a verify register coupled to compare logic, said verify register coupled to said control logic and said serial input port, said compare logic coupled to said memory location and said data storage element, wherein said control logic controls when verify data is read from said memory location and compared with said program data by said compare logic.

Claim 31

Dependent Claim 167 words

A test circuit in a programmable logic device having a memory location, said test circuit comprising: a serial input port; an address storage element coupled to said serial input port, said address storage element receiving address information corresponding to said memory location from said serial input port; a data storage element coupled to said serial input port, said data storage element receiving program data from said serial input port; control logic coupled to said address storage element and said data storage element, said control logic controlling when said program data is programmed into said memory location addressed by said address information; and verify logic coupled to said data storage element, said memory location and a clock signal, said verify logic receiving verify data read from said memory location, said control logic controlling when said verify data is read from said memory location, said verify logic comparing said verify data and said program data and generating a comparison result in response to a transition of said clock signal.

Claim 32

Dependent Claim 167 words

A test circuit in a programmable logic device having a memory location, said test circuit comprising: a serial input port; an address storage element coupled to said serial input port, said address storage element receiving address information corresponding to said memory location from said serial input port; a data storage element coupled to said serial input port, said data storage element receiving program data from said serial input port; control logic coupled to said address storage element and said data storage element, said control logic controlling when said program data is programmed into said memory location addressed by said address information; and verify logic coupled to said data storage element, said memory location and a clock signal, said verify logic receiving verify data read from said memory location, said control logic controlling when said verify data is read from said memory location, said verify logic comparing said verify data and said program data and generating a comparison result in response to a transition of said clock signal.

Claim 33

Independent Claim 61 words

A method for programming a programmable logic device comprising: loading address information into said programmable logic device; loading program data into said programmable logic device; programming said program data into a memory location defined by said address information; verifying whether said program data was programmed correctly into said memory location, wherein said verifying step uses said program data as a mask.

Claim 34

Independent Claim 61 words

A method for programming a programmable logic device comprising: loading address information into said programmable logic device; loading program data into said programmable logic device; programming said program data into a memory location defined by said address information; verifying whether said program data was programmed correctly into said memory location, wherein said verifying step uses said program data as a mask.

Claim 35

Dependent Claim 26 words

The method of claim 30, wherein the verifying step comprises: reading verify data from said memory location; and comparing said program data with said verify data.

Claim 36

Dependent Claim 60 words

The method of claim 31, further comprising the steps of: generating an output signal in response to the comparing step, the output signal indicating whether said program data matches said verify data; and repeating the programming and verifying steps when the output signal indicates that said program data does not match said verify data or when a predetermined event occurs.

Claim 37

Dependent Claim 21 words

The method of claim 32, wherein the predetermined event comprises performing the programming and verifying steps a predetermined number of times.

Claim 38

Dependent Claim 25 words

The method of claim 32, wherein said program data matches said verify data when said program data and said verify data comprise equivalent logic states.

Claim 39

Dependent Claim 25 words

The method of claim 32, wherein said program data matches said verify data when said program data and said verify data comprise different logic states.

Claim 40

Dependent Claim 73 words

The method of claim 32, further comprising the steps of: generating a plurality of match signals in response to said comparing step, said plurality of match signals indicating whether said program data matches said verify data; comparing said program data with said plurality of match signals and generating a plurality of mask result signals in response thereto; and receiving said plurality of mask result signals and generating a verify signal in response thereto.

Claim 41

Dependent Claim 18 words

The method of claim 36, further comprising the step of: providing said verify signal as said output signal.

Claim 42

Dependent Claim 27 words

The method of claim 37, further comprising the step of: providing said verify signal as said output signal in response to a transition of a clock signal.

Claim 43

Dependent Claim 136 words

A self-masking circuit comprising: a first logic block having: a first plurality of logic elements coupled to a first plurality of data bits and a second plurality of data bits, said first plurality of logic elements logically comparing the first plurality of data bits and the second plurality of data bits and generating a plurality of match signals in response to the comparison; a second plurality of logic elements coupled to the first plurality of logic elements, said second plurality of logic elements logically comparing the first plurality of data bits and the plurality of match signals and generating a plurality of mask result signals in response to the comparison; and a second logic block having a verify logic element, said verify logic element receiving said plurality of mask result signals and generating a verify signal.

Claim 44

Dependent Claim 136 words

A self-masking circuit comprising: a first logic block having: a first plurality of logic elements coupled to a first plurality of data bits and a second plurality of data bits, said first plurality of logic elements logically comparing the first plurality of data bits and the second plurality of data bits and generating a plurality of match signals in response to the comparison; a second plurality of logic elements coupled to the first plurality of logic elements, said second plurality of logic elements logically comparing the first plurality of data bits and the plurality of match signals and generating a plurality of mask result signals in response to the comparison; and a second logic block having a verify logic element, said verify logic element receiving said plurality of mask result signals and generating a verify signal.

Claim 45

Dependent Claim 44 words

The self-masking circuit of claim 39, wherein: each of said first plurality of logic elements provides an exclusive OR (XOR) function; each of said second plurality of logic elements provides an AND function; and said verify logic element provides an inverted OR (NOR) function.

Claim 46

Dependent Claim 140 words

A self-masking circuit comprising: a first logic block having a plurality of logic elements, said plurality of logic elements receiving a first plurality of data bits and a second plurality of data bits, said plurality of logic elements logically comparing the first plurality of data bits with the second plurality of data bits and generating a plurality of mask result signals in response to the comparison, said first plurality of data bits operating as a mask on said comparison of said first plurality of data bits with said second plurality of data bits such that only those bits in the first plurality of data bits comprising a predetermined logic state participate in the comparison; and a second logic block having a verify logic element, said verify logic element receiving said plurality of mask result signals and generating a verify signal.

Claim 47

Dependent Claim 140 words

A self-masking circuit comprising: a first logic block having a plurality of logic elements, said plurality of logic elements receiving a first plurality of data bits and a second plurality of data bits, said plurality of logic elements logically comparing the first plurality of data bits with the second plurality of data bits and generating a plurality of mask result signals in response to the comparison, said first plurality of data bits operating as a mask on said comparison of said first plurality of data bits with said second plurality of data bits such that only those bits in the first plurality of data bits comprising a predetermined logic state participate in the comparison; and a second logic block having a verify logic element, said verify logic element receiving said plurality of mask result signals and generating a verify signal.

Claim 48

Dependent Claim 29 words

The self-masking circuit of claim 41, wherein: each of said plurality of logic elements provides an AND function and said verify logic element provides an inverted OR (NOR) function.

Claim 49

Dependent Claim 33 words

The self-masking circuit of claim 41, wherein: each of said first plurality of logic elements provides an inverted OR (NOR) function and said verify logic block element provides an inverted OR (NOR) function.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2001-06-15	2001-12-15	2002-06-16	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2005-06-15	2005-12-15	2006-06-16	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2009-06-15	2009-12-15	2010-06-16	$7700.00	Window Closed / Lapsed

Method and apparatus for programming a programmable logic device having verify logic for comparing verify data read from a memory location with program data

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