Patent US5768152A successfully refreshed from Google Patents.
US5768152A
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Performance monitoring through JTAG 1149.1 interface
Assignee: Cavium International
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Filing: 1996-08-28
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Granted: 1998-06-16
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Expires: 2016-08-28
Abstract
Abstract Disclosed is a system and method of providing performance analysis on integrated circuit devices and systems using an IEEE JTAG 1149.1 interface. An integrated circuit device is described that includes an execution control register for receiving a control code from an external device via the JTAG interface, a means for selecting and coupling to one or more specific logic circuits on the device, one or more counters for recording specific events occurring on the logic circuits, and a counter register for managing the counter data and outputting it via the JTAG interface.
Inventors
- 👤 Robert P. Battaline
- 👤 James R. Robinson
- 👤 Edward H. Welbon
- 👤 Ralph J. Williams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:47
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/3466; G06F11/348; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G06F11/3409; G06F2201/00; G06F2201/86; G06F2201/88
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
153 words
A computer apparatus having a system for monitoring performance, said apparatus having a plurality of integrated circuit devices serially connected to a JTAG 1149.1 compliance port, each said integrated circuit device comprising: a JTAG 1149.1 compliant interface; an event monitor control register coupled to said JTAG 1149.1 compliant interface, said event monitor control register for storing a control code downloaded via said JTAG 1149.1 compliant interface; a control system, said control system including logic to read said control code and select and couple to one of a plurality of circuits on said first integrated circuit device; a counter, said counter for reading and accumulating signals occurring on said one of said plurality of circuits on said first integrated circuit device; and an event count register coupled to said JTAG 1149.1 compliant interface, said event count register for reading a total count from said counter and outputting it via said JTAG 1149.1 compliant interface.
Claim 2
Dependent Claim
153 words
A computer apparatus having a system for monitoring performance, said apparatus having a plurality of integrated circuit devices serially connected to a JTAG 1149.1 compliance port, each said integrated circuit device comprising: a JTAG 1149.1 compliant interface; an event monitor control register coupled to said JTAG 1149.1 compliant interface, said event monitor control register for storing a control code downloaded via said JTAG 1149.1 compliant interface; a control system, said control system including logic to read said control code and select and couple to one of a plurality of circuits on said first integrated circuit device; a counter, said counter for reading and accumulating signals occurring on said one of said plurality of circuits on said first integrated circuit device; and an event count register coupled to said JTAG 1149.1 compliant interface, said event count register for reading a total count from said counter and outputting it via said JTAG 1149.1 compliant interface.
Claim 3
Dependent Claim
18 words
The computer apparatus of claim 1 wherein said event monitor control register is an existing JTAG 1149.1 register.
Claim 4
Dependent Claim
17 words
The computer apparatus of claim 1 wherein said event count register is an existing JTAG 1149.1 register.
Claim 5
Dependent Claim
17 words
The computer apparatus of claim 1 wherein said first integrated circuit device includes a plurality of counters.
Claim 6
Dependent Claim
21 words
The computer apparatus of claim 1 wherein said counter runs synchronous to a system clock on said first integrated circuit device.
Claim 7
Dependent Claim
24 words
The computer apparatus of claim 1 wherein said event monitor control register includes means for defining which of said plurality of circuits to monitor.
Claim 8
Dependent Claim
25 words
The computer apparatus of claim 4 wherein said event monitor control register includes means for defining an event for each of said plurality of counters.
Claim 9
Dependent Claim
18 words
The computer apparatus of claim 1 wherein said event monitor control register includes means for enabling said counter.
Claim 10
Dependent Claim
139 words
An integrated circuit device having performance monitoring capabilities, comprising: a JTAG 1149.1 compliant interface; an external device, said external device for downloading a control code via said JTAG 1149.1 compliant interface: means for storing said control code inputted via said JTAG 1149.1 compliant interface; control means for selecting and coupling to at least one of a plurality of circuits on said integrated circuit device based upon said control code; counting means coupled to said control means, said counting means for monitoring signals on said at least one of said plurality of circuits and accumulating a total count for each of said at least one of said plurality of circuits and accumulating a total count for each of said at least one of said plurality of circuits; and means for outputting said total count via said JTAG 1149.1 compliant interface.
Claim 11
Dependent Claim
139 words
An integrated circuit device having performance monitoring capabilities, comprising: a JTAG 1149.1 compliant interface; an external device, said external device for downloading a control code via said JTAG 1149.1 compliant interface: means for storing said control code inputted via said JTAG 1149.1 compliant interface; control means for selecting and coupling to at least one of a plurality of circuits on said integrated circuit device based upon said control code; counting means coupled to said control means, said counting means for monitoring signals on said at least one of said plurality of circuits and accumulating a total count for each of said at least one of said plurality of circuits and accumulating a total count for each of said at least one of said plurality of circuits; and means for outputting said total count via said JTAG 1149.1 compliant interface.
Claim 12
Dependent Claim
21 words
The integrated circuit device of claim 9 wherein said means for storing a control code includes an event monitor control register.
Claim 13
Dependent Claim
14 words
The integrated circuit device of claim 9 wherein said control means includes a multiplexor.
Claim 14
Dependent Claim
27 words
The integrated circuit device of claim 9 wherein said counting means includes at least one counter be driven by a clock operating synchronously with a system clock.
Claim 15
Dependent Claim
20 words
The integrated circuit device of claim 9 wherein said means for outputting said total count includes an event count register.
Claim 16
Independent Claim
133 words
A method for monitoring events on an integrated circuit device wherein said integrated circuit device includes a JTAG 1149.1 compliant interface and a control system for monitoring a plurality of circuits, said method comprising the steps of: using an external device to select a first event to monitor; downloading a control code from said external device to said integrated circuit device via said JTAG 1149.1 compliant interface; writing said control code to an event monitor control register located in said integrated circuit device; selecting and electrically coupling to one of said plurality of circuits; accumulating in a counter occurrences of electrical signals at one of said plurality of circuits; loading a total count in an event count register; and outputting said total count to said external device via said JTAG 1149.1 compliant interface.
Claim 17
Independent Claim
133 words
A method for monitoring events on an integrated circuit device wherein said integrated circuit device includes a JTAG 1149.1 compliant interface and a control system for monitoring a plurality of circuits, said method comprising the steps of: using an external device to select a first event to monitor; downloading a control code from said external device to said integrated circuit device via said JTAG 1149.1 compliant interface; writing said control code to an event monitor control register located in said integrated circuit device; selecting and electrically coupling to one of said plurality of circuits; accumulating in a counter occurrences of electrical signals at one of said plurality of circuits; loading a total count in an event count register; and outputting said total count to said external device via said JTAG 1149.1 compliant interface.
Claim 18
Dependent Claim
13 words
The method of claim 14 wherein said external device includes an in-circuit emulator.
Claim 19
Dependent Claim
22 words
The method of claim 14 wherein the step of writing said control code to an event monitor control register is done serially.
Claim 20
Dependent Claim
21 words
The method of claim 14 wherein said control code defines which of said plurality of circuits to select and couple to.
Claim 21
Dependent Claim
13 words
The method of claim 14 further comprising the step of enabling the counter.
Claim 22
Dependent Claim
23 words
The method of claim 14 further comprising the step of selecting and electrically coupling to more than one of said plurality of circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-15 | 2001-12-15 | 2002-06-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-15 | 2005-12-15 | 2006-06-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-15 | 2009-12-15 | 2010-06-16 | $7700.00 | Window Closed / Lapsed |