Test access port controlled built in current monitor for IC devices

Claim 2

An integrated circuit (IC) device comprising: a MOS or CMOS circuit module coupled between high and low potential power rails; a built in current (BIC) monitor coupled between the MOS or CMOS circuit module and a low potential power rail for monitoring the level of static or quiescent current (IDDQ), said BIC monitor being constructed to provide a digital code fault signal at an output according to the monitored level of static current (IDDQ); a test access port (TAP) with TAP access pins including a TAP data input (TDI) pin and a TAP data output (TDO) pin, said test access port having a plurality of TAP data registers (TDR's) coupled to receive data signals at the TDI pin and to shift data signals to the TDO pin, said TDR's including a boundary scan register (BSR/TDR1) for applying test vectors at data inputs of the IC device for performing boundary scan testing, a TAP instruction register (TIR) coupled to receive instruction codes at the TDI pin and to direct use of selected TDR's, and a TAP controller coupled to receive control and clock signals and to direct control and clock signals controlling operation of the TIR and TDR's; a bypass or shunt MOS transistor having primary current path coupled in parallel with the BIC monitor between the MOS or CMOS circuit module and low potential power rail; said TDR's comprising a design specific BIC shunt control TDR (BICSC TDR) constructed for receiving a coded BIC monitor bypass code (BICBC) at the TDI pin, said BICSC TDR having an output coupled to a control node of the MOS bypass or shunt transistor for controlling the conducting state of the MOS bypass or shunt transistor according to the BIC monitor bypass code (BICBC); said MOS bypass or shunt transistor providing a low impedance bypass path around the BIC monitor in response to a first BICBC during normal operation of the IC device, said MOS bypass or shunt transistor presenting a high impedance bypass path in response to a second BICBC for monitoring quiescent current at the BIC monitor.

Claim 3

The IC device of claim 1 wherein the TDR's comprise a design specific BIC fault capture TDR (BICFCP TDR) coupled to an output of the BIC monitor for receiving and storing digitally coded fault signals according to the monitored level of static current and for shifting out digitally coded fault signals to the TDO pin.

Claim 4

The IC device of claim 2 wherein the TDR's of the test access port comprise a design specific IDDQ test vector (ITV) TDR coupled to internal nodes of the IC device CMOS circuit module, said ITV TDR being coupled to receive IDDQ test vectors at the TDI pin and to apply IDDQ test vectors at selected nodes of the MOS or CMOS circuit module for testing and sensing the level of static current IDDQ at the BIC monitor in response to application of the IDDQ test vectors.

Claim 5

The IC device of claim 2 wherein the IC device comprises a plurality of MOS or CMOS circuit modules, a plurality of BIC monitors coupled between the respective MOS or CMOS circuit modules and the low potential power rail, and a plurality of bypass or shunt MOS transistors having primary current paths coupled in parallel with the respective BIC monitors; wherein the design specific BIC shunt control TDR (BICSC TDR) comprises a serial port input coupled to the TDI pin for receiving a coded BIC monitor bypass code (BICBC) for selectively controlling the plurality of bypass or shunt MOS transistors, and a parallel output port having parallel outputs coupled to respective control nodes of the plurality of MOS bypass or shunt transistors; and wherein the BIC fault capture TDR (BICFCP TDR) comprises a serial port output coupled to the TDO pin and a parallel port input having parallel inputs coupled to respective outputs of the plurality of BIC monitors for receiving and storing digitally coded fault signals and for shifting out digitally coded fault signals to the TDO pin.

Claim 6

The IC device of claim 4 wherein the TDR's of the test access port comprise a design specific IDDQ test vector (ITV) TDR coupled to internal nodes of the IC device MOS or CMOS circuit module, said ITV TDR being coupled to receive IDDQ test vectors at the TDI pin and to apply the IDDQ test vectors at selective nodes of the CMOS circuit module for testing and sensing the level of static current IDDQ at the BIC monitor in response to application of the IDDQ test vectors.

Claim 7

The integrated circuit device of claim 1 wherein the IC device comprises: a plurality of MOS or CMOS circuit modules; a plurality of BIC monitors coupled between the respective MOS or CMOS circuit modules and low potential power rail; and a plurality of MOS bypass or shunt transistors having primary current paths coupled in parallel with respective BIC monitors; wherein the design specific BIC shunt control TDR (BICSC TDR) comprises a serial port input coupled to the TDI pin for receiving a coded BIC monitor bypass code (BICBC) at the TDI pin for controlling the respective MOS bypass or shunt transistors, and a parallel output port having parallel outputs coupled to respective control nodes of the plurality of MOS bypass or shunt transistors; and wherein the BIC shunt control TDR (BICSC TDR) further comprises a BIC fault capture TDR (BICFCP TDR) as a single BIC control TAP data register (BICC TDR), said BICC TDR further comprising a serial port output coupled to the TDO pin and a parallel port input having parallel inputs coupled to respective outputs of the plurality of BIC monitors for receiving and storing digitally coded fault signals according to the monitored level of static current in the respective MOS or CMOS circuit modules and for shifting out digitally coded fault signals to the TDO pin.

Claim 8

The IC device of claim 6 wherein the TDR's of the test access port comprise a design specific IDDQ test vector (ITV) TDR coupled to internal nodes of the IC device MOS or CMOS circuit module, said ITV TDR being coupled to receive IDDQ test vectors at the TDI pin and to apply the IDDQ test vectors at selective nodes of the MOS or CMOS circuit module for testing and sensing the level of static current IDDQ at the BIC monitor 10 in response to application of the IDDQ test vectors.

Claim 9

An integrated circuit device having CMOS circuit modules coupled between high and low potential power rails, at least one built-in current (BIC) monitor coupled between a CMOS circuit module and low potential power rail for monitoring the level of static or quiescent current (IDDQ) said BIC monitor being constructed to provide a digital code fault signal at an output according to the monitored level of static current (IDDQ), and a test access port (TAP) with TAP access pins including a TAP data input (TDI) pin and a TAP data output (TDO) pin, said test access port having a plurality of TAP data registers (TDR's) coupled to receive data signals at the TDI pin and to shift data signals to the TDO pin, said TDR's including a boundary scan register (BSR/TDR1) for applying test vectors at data inputs of the IC device for performing boundary scan testing, a TAP instruction register (TIR) coupled to receive instruction codes at the TDI pin and to direct use of selected TDR's, and a TAP controller coupled to receive control and clock signals and to direct control and clock signals controlling operation of the TIR and TDR's, comprising: a MOS bypass transistor having a primary current path coupled in parallel with the BIC monitor between the CMOS circuit module and low potential power rail; said TDR's comprising a design specific BIC shunt control TDR (BICSC TDR) constructed for receiving a coded BIC monitor bypass code (BICBC) at the TDI pin, said BICSC TDR having an output coupled to a control node of the MOS bypass transistor for controlling a conducting state of the MOS bypass transistor according to the coded BIC monitor bypass code (BICBC); said MOS bypass transistor providing a low impedance bypass path around the BIC monitor in response to a first BICBC during normal operation of the IC device, said MOS bypass transistor presenting a high impedance bypass path in response to a second BICBC for monitoring the level of static current (IDDQ) at the BIC monitor; said TDR's also comprising a design specific BIC fault capture TDR (BICFCP TDR) coupled to an output of the BIC monitor for receiving and storing digitally coded fault signals according to the monitored level of static current (IDDQ) and for shifting out fault signals to the TDO pin.

Claim 10

An integrated circuit device having CMOS circuit modules coupled between high and low potential power rails, at least one built-in current (BIC) monitor coupled between a CMOS circuit module and low potential power rail for monitoring the level of static or quiescent current (IDDQ) said BIC monitor being constructed to provide a digital code fault signal at an output according to the monitored level of static current (IDDQ), and a test access port (TAP) with TAP access pins including a TAP data input (TDI) pin and a TAP data output (TDO) pin, said test access port having a plurality of TAP data registers (TDR's) coupled to receive data signals at the TDI pin and to shift data signals to the TDO pin, said TDR's including a boundary scan register (BSR/TDR1) for applying test vectors at data inputs of the IC device for performing boundary scan testing, a TAP instruction register (TIR) coupled to receive instruction codes at the TDI pin and to direct use of selected TDR's, and a TAP controller coupled to receive control and clock signals and to direct control and clock signals controlling operation of the TIR and TDR's, comprising: a MOS bypass transistor having a primary current path coupled in parallel with the BIC monitor between the CMOS circuit module and low potential power rail; said TDR's comprising a design specific BIC shunt control TDR (BICSC TDR) constructed for receiving a coded BIC monitor bypass code (BICBC) at the TDI pin, said BICSC TDR having an output coupled to a control node of the MOS bypass transistor for controlling a conducting state of the MOS bypass transistor according to the coded BIC monitor bypass code (BICBC); said MOS bypass transistor providing a low impedance bypass path around the BIC monitor in response to a first BICBC during normal operation of the IC device, said MOS bypass transistor presenting a high impedance bypass path in response to a second BICBC for monitoring the level of static current (IDDQ) at the BIC monitor; said TDR's also comprising a design specific BIC fault capture TDR (BICFCP TDR) coupled to an output of the BIC monitor for receiving and storing digitally coded fault signals according to the monitored level of static current (IDDQ) and for shifting out fault signals to the TDO pin.

Claim 11

The IC device of claim 8 wherein the TDR's of the test access port comprise a design specific IDDQ test vector (ITV) TDR coupled to internal nodes of the IC device CMOS circuit module, said ITV TDR being coupled to receive IDDQ test vectors at the TDI pin and to apply the IDDQ test vectors at selective nodes of the CMOS circuit module for testing and sensing the level of static current IDDQ at the BIC monitor in response to application of the IDDQ test vectors.

Claim 14

The method of claim 10 further comprising the step of storing digitally coded fault signals from the output of the BIC monitor according to the monitored level of static current (IDDQ) from the MOS or CMOS circuit module using a design specific BIC fault capture TDR (BICFCP TDR) of the test access port and shifting out fault signals from the BICFCP TDR to the TDO pin.

Claim 15

The method of claim 11 comprising the further steps: applying a test vector for monitoring and testing static current (IDDQ) from the MOS or CMOS circuit module by using a design specific IDDQ test vector (ITV) TDR of the test access port (TAP) coupled to internal nodes of the MOS or CMOS circuit module and sensing and measuring the level of IDDQ at the BIC monitor after applying the test vector.

Claim 16

The method of claim 11 wherein the bypass or shunt circuit is a MOS bypass transistor having a primary current path coupled in parallel with the BIC monitor and wherein the BICSC TDR is coupled to a control gate node of the MOS bypass transistor.

Claim 17

The method of claim 13 comprising: a plurality of MOS or CMOS circuit modules; monitoring static current (IDDQ) from said plurality of MOS or CMOS circuit modules using a plurality of BIC monitors coupled between the respective MOS or CMOS circuit modules and the low potential power rail, and using a plurality of bypass MOS transistors having primary current paths coupled in parallel with the respective BIC monitors; controlling conducting states of the plurality of bypass MOS transistors using a design specific BIC shunt control TDR (BICSC TDR) having a serial port input coupled to the TDI pin for receiving a coded BIC monitor bypass code (BICBC) for selectively controlling the plurality of bypass MOS transistors and a parallel output port having parallel outputs coupled to respective control nodes of the plurality of MOS bypass transistors; and receiving digitally coded fault signals (F) from the outputs of the plurality of BIC monitors using a BIC fault capture TDR (BICFCP TDR) having a serial port output coupled to the TDO pin and a parallel port input coupled to respective outputs of the plurality of BIC monitors for receiving and storing digitally coded fault signals and for shifting out digitally coded fault signals to the TDO pin.

Claim 18

An integrated circuit device comprising: a MOS or CMOS circuit module coupled between high and low potential power rails; a built in current (BIC) monitor coupled between the MOS or CMOS circuit module and low potential power rail for monitoring the level of static or quiescent current (IDDQ), said BIC monitor being constructed to provide a digital code fault signal at an output according to the monitored level of static or quiescent current (IDDQ); a test access port (TAP) with TAP access pins including a TAP data input (TDI) pin and a TAP data output (TDO) pin, said test access port having a plurality of TAP data registers (TDR's) coupled to receive data signals at the TDI pin and to shift data signals to the TDO pin, said TDR's including a boundary scan register (BSR/TDR1) for applying test vectors at data inputs of the IC device for performing boundary scan testing, a TAP instruction register (TIR) coupled to receive instruction codes at the TDI pin and to direct use of selected TDR's, and a TAP controller coupled to receive control and clock signals and to direct control and clock signals controlling operation of the TIR and selected TDR's; a bypass or shunt circuit coupled in parallel with the BIC monitor between the MOS or CMOS circuit module and low potential power rail said bypass or shunt circuit having a low impedance conducting state and a high impedance conducting state and control means for controlling the conducting state of the bypass or shunt circuit; said TDR's comprising a design specific BIC shunt control TDR (BICSC TDR) constructed for receiving a coded BIC monitor bypass code (BICBC) at the TDI pin, said BICSC TDR having an output coupled to the control means for controlling the conducting state of the bypass or shunt circuit according to the coded BIC monitor bypass code (BICBC); said bypass or shunt circuit providing a low impedance bypass path around the BIC monitor in response to a first BICBC during normal operation of the IC device, said bypass circuit presenting a high impedance bypass path in response to a second BICBC for monitoring the level of static or quiescent current (IDDQ) at the BIC monitor.

Claim 19

An integrated circuit device comprising: a MOS or CMOS circuit module coupled between high and low potential power rails; a built in current (BIC) monitor coupled between the MOS or CMOS circuit module and low potential power rail for monitoring the level of static or quiescent current (IDDQ), said BIC monitor being constructed to provide a digital code fault signal at an output according to the monitored level of static or quiescent current (IDDQ); a test access port (TAP) with TAP access pins including a TAP data input (TDI) pin and a TAP data output (TDO) pin, said test access port having a plurality of TAP data registers (TDR's) coupled to receive data signals at the TDI pin and to shift data signals to the TDO pin, said TDR's including a boundary scan register (BSR/TDR1) for applying test vectors at data inputs of the IC device for performing boundary scan testing, a TAP instruction register (TIR) coupled to receive instruction codes at the TDI pin and to direct use of selected TDR's, and a TAP controller coupled to receive control and clock signals and to direct control and clock signals controlling operation of the TIR and selected TDR's; a bypass or shunt circuit coupled in parallel with the BIC monitor between the MOS or CMOS circuit module and low potential power rail said bypass or shunt circuit having a low impedance conducting state and a high impedance conducting state and control means for controlling the conducting state of the bypass or shunt circuit; said TDR's comprising a design specific BIC shunt control TDR (BICSC TDR) constructed for receiving a coded BIC monitor bypass code (BICBC) at the TDI pin, said BICSC TDR having an output coupled to the control means for controlling the conducting state of the bypass or shunt circuit according to the coded BIC monitor bypass code (BICBC); said bypass or shunt circuit providing a low impedance bypass path around the BIC monitor in response to a first BICBC during normal operation of the IC device, said bypass circuit presenting a high impedance bypass path in response to a second BICBC for monitoring the level of static or quiescent current (IDDQ) at the BIC monitor.

Claim 20

The IC device of claim 15 wherein the TDR's comprise a design specific BIC fault capture TDR (BICFCP TDR) coupled to the output of the BIC monitor for receiving and storing digitally coded fault signals according to the monitored level of static current IDDQ and for shifting out digitally coded fault signals to the TDO pin.

Claim 21

The IC device of claim 16 wherein the TDR's of the test access port comprise a design specific IDDQ test vector (ITV) TDR coupled to internal nodes of the IC device MOS or CMOS circuit module, said ITV TDR being coupled to receive IDDQ test vectors at the TDI pin and to apply IDDQ test vectors at selected nodes of the CMOS circuit module for testing and sensing the level of static current IDDQ at the BIC monitor in response to application of the IDDQ test vectors.

Claim 22

The IC device of claim 15 wherein the bypass or shunt circuit comprises a bypass MOS transistor having primary current path coupled in parallel with the BIC monitor and wherein the control means comprises a control gate node of the bypass MOS transistor.