US5428624A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fault injection using boundary scan
Assignee: Storage Technology Corp
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Filing: 1993-10-12
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Granted: 1995-06-27
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Expires: 2013-10-12
Abstract
Abstract A system and method for fault injection utilizing boundary scan includes the provision of an additional fault injection register to the standard JTAG architecture in order to allow the intentional introduction of faults into a device or module forming part of a system under test. Through the use of the fault injection register of the present invention, faults may be intentionally introduced and the system response to such faults monitored and analyzed independently of the system software and without the use of mechanical probes or the like for introducing the fault. The system and method of the present invention is readily integrated with the existing test functions of the standard IEEE 1149.1 boundary scan architecture.
Inventors
- 👤 Larry D. Blair
- 👤 John C. Joy
- 👤 William H. Dittenhofer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:32
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/318547; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
261 words
A diagnostics system for validating diagnostic circuitry of an electrical circuit having at least a first system card and a second system card wherein the first and second system cards, respectively, each are operative to perform identical functions, said diagnostics system comprising: a first system interface disposed together with the first system card, said first system interface having a first boundary scan circuit incorporating first test access port state machine in operative association with a first instruction register, a first boundary scan register, a first bypass register, and a first fault injection register, the first fault injection register for selectably injecting a fault vector to first circuitry of the first system card; a second system interface disposed together with the second system card, said second system interface having a second boundary scan circuit incorporating a second test access port state machine in operative association with a second instruction register, a second boundary scan register, a second bypass register, and a second fault injection register, the second fault injection register for selectably injecting the fault vector to second circuitry of the second system card; and system software operative responsive to the fault vector, when injected to the first circuitry of the first system card, to isolate the first system card and to assign functioning of the first system card to the second system card and operative responsive to the fault vector when injected to the second circuitry of the second system card, to isolate the second system card and the assign functioning of the second system card to the first system card.
Claim 2
Dependent Claim
261 words
A diagnostics system for validating diagnostic circuitry of an electrical circuit having at least a first system card and a second system card wherein the first and second system cards, respectively, each are operative to perform identical functions, said diagnostics system comprising: a first system interface disposed together with the first system card, said first system interface having a first boundary scan circuit incorporating first test access port state machine in operative association with a first instruction register, a first boundary scan register, a first bypass register, and a first fault injection register, the first fault injection register for selectably injecting a fault vector to first circuitry of the first system card; a second system interface disposed together with the second system card, said second system interface having a second boundary scan circuit incorporating a second test access port state machine in operative association with a second instruction register, a second boundary scan register, a second bypass register, and a second fault injection register, the second fault injection register for selectably injecting the fault vector to second circuitry of the second system card; and system software operative responsive to the fault vector, when injected to the first circuitry of the first system card, to isolate the first system card and to assign functioning of the first system card to the second system card and operative responsive to the fault vector when injected to the second circuitry of the second system card, to isolate the second system card and the assign functioning of the second system card to the first system card.
Claim 3
Dependent Claim
23 words
The diagnostics system of claim 1 wherein said first test access port state machine receives test mode select and test clock input signals.
Claim 4
Dependent Claim
23 words
The diagnostics system of claim 1 wherein said second test access port state machine receives test mode select and test clock input signals.
Claim 5
Independent Claim
174 words
A method for validating diagnostic circuits of an electrical circuit having at least a first system card and a second system card wherein the first and second system cards, respectively, each are operative to perform identical functions, said method comprising the steps of: selectably injecting a fault vector through a first fault injection register which forms a portion of a first boundary scan circuit disposed together with the first system card to first circuitry of the first system card; selectably injecting the fault vector through a second fault injection register which forms a portion of a second boundary scan circuit disposed together with the second system card to second circuitry of the second system card; isolating the first system card and assigning functioning of the first system card to the second system card responsive to injection of the fault vector to the first circuitry; and isolating the second system card and assigning functioning of the second system card to the first system card responsive to injection of the fault vector to the second circuitry.
Claim 6
Independent Claim
174 words
A method for validating diagnostic circuits of an electrical circuit having at least a first system card and a second system card wherein the first and second system cards, respectively, each are operative to perform identical functions, said method comprising the steps of: selectably injecting a fault vector through a first fault injection register which forms a portion of a first boundary scan circuit disposed together with the first system card to first circuitry of the first system card; selectably injecting the fault vector through a second fault injection register which forms a portion of a second boundary scan circuit disposed together with the second system card to second circuitry of the second system card; isolating the first system card and assigning functioning of the first system card to the second system card responsive to injection of the fault vector to the first circuitry; and isolating the second system card and assigning functioning of the second system card to the first system card responsive to injection of the fault vector to the second circuitry.
Claim 7
Dependent Claim
92 words
The diagnostics system of claim 2 wherein said first test access port state machine receives the test mode select and test clock input signals and selectively couples a test data input signal to a test data output signal and wherein said first fault injection register is selectable by said first instruction register for coupling said test data input signal to said test data output signal, said first fault injection register being responsive to said first test access port state machine and said first instruction register for generating a fault injunction control signal.
Claim 8
Dependent Claim
92 words
The diagnostics system of claim 3 wherein said second test access port state machine receives the test mode select and test clock input signals and selectively couples a test data input signal to a test data output signal and wherein said second fault injection register is selectable by said second instruction register for coupling said test data input signal to said test data output signal, said second fault injection register being responsive to said second test access port state machine and said second instruction register for generating a fault injection control signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-26 | 1998-12-26 | 1999-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-26 | 2002-12-26 | 2003-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-26 | 2006-12-26 | 2007-06-27 | $7700.00 | Window Closed / Lapsed |