Voltage controlled ring oscillator frequency multiplier

Claim 2

A voltage controlled ring oscillator having harmonic frequency components, the oscillator comprising: a first, second and third inverter each with an input and an output, the output of the first inverter electrically coupled with the input of the second inverter, the output of the second inverter electrically coupled with the input of the third inverter, the output of the third inverter electrically coupled with the input of the first inverter; and a first, second and third summing component, the summing components each having one end electrically coupled to an output of the first, second and third inverters, respectively, the other ends of the summing components being commonly electrically connected at a common harmonic frequency output node; the output of the third inverter providing a fundamental output frequency; the summing components passively coupling the harmonic frequency components of ring oscillator such that constructive summation of harmonic frequency components occurs for those frequency components, F(t), of a multiple n, being an odd multiple of three in accordance with the formula F(t)=a.sub.n cos (n(ωt)) where (n=3, 9, 15, . . . ); the constructively summed harmonic frequency components being provided at the common harmonic frequency output node, the third-harmonic frequency component at the common harmonic frequency output node having the highest amplitude.

Claim 3

The ring oscillator of claim 1, wherein each summing component is selected from at least one of the group consisting of resistors, capacitors and inductors.

Claim 4

The ring oscillator of claim 2, wherein the summing components are capacitors.

Claim 5

The ring oscillator of claim 1, wherein the third-harmonic frequency output is electrically coupled to a discrete power transistor to provide a buffered third-harmonic frequency signal.

Claim 6

The ring oscillator of claim 1, wherein the ring oscillator is provided on an integrated circuit.

Claim 7

The ring oscillator of claim 1, wherein a multiplied frequency is provided having a period approaching approximately two inverter propagation delays.

Claim 8

A frequency synthesizer including a reference oscillator coupled to a frequency translational element providing a translated signal, comprising: a locked loop circuit and detector chosen from the group consisting of a phase locked loop with a phase detector, a frequency locked loop with a frequency detector and a delay locked loop with a delay detector; the translated signal being coupled to a first input of the detector of the locked loop circuit, the detector providing a control voltage; and a voltage controlled ring oscillator having harmonic frequency components, the oscillator comprising: a first, second and third inverter each with an input and an output, the output of the first inverter electrically coupled with the input of the second inverter, the output of the second inverter electrically coupled with the input of the third inverter, the output of the third inverter electronically coupled with the input of the first inverter, propagation delays of each inverter controlled by the control voltage; and a first, second and third summing component, the summing components each having one end electrically coupled to an output of the first, second and third inverters respectively, the other ends of the summing components being commonly electrically connected at a common harmonic frequency output node; the output of the third inverter providing a fundamental output frequency applied to a second input of the detector; the summing components passively coupling the harmonic frequency components of ring oscillator such that constructive summation of harmonic frequency components occurs for those frequency components, F(t), of a multiple, n, being an odd multiple of three in accordance with the formula F(t)=a.sub.n cos (n(ωt)) where (n=3, 9, 15, . . . ); the constructively summed harmonic frequency components being provided at the common harmonic frequency output node, the third-harmonic frequency component at the common harmonic frequency output node having the highest amplitude.

Claim 9

A frequency synthesizer including a reference oscillator coupled to a frequency translational element providing a translated signal, comprising: a locked loop circuit and detector chosen from the group consisting of a phase locked loop with a phase detector, a frequency locked loop with a frequency detector and a delay locked loop with a delay detector; the translated signal being coupled to a first input of the detector of the locked loop circuit, the detector providing a control voltage; and a voltage controlled ring oscillator having harmonic frequency components, the oscillator comprising: a first, second and third inverter each with an input and an output, the output of the first inverter electrically coupled with the input of the second inverter, the output of the second inverter electrically coupled with the input of the third inverter, the output of the third inverter electronically coupled with the input of the first inverter, propagation delays of each inverter controlled by the control voltage; and a first, second and third summing component, the summing components each having one end electrically coupled to an output of the first, second and third inverters respectively, the other ends of the summing components being commonly electrically connected at a common harmonic frequency output node; the output of the third inverter providing a fundamental output frequency applied to a second input of the detector; the summing components passively coupling the harmonic frequency components of ring oscillator such that constructive summation of harmonic frequency components occurs for those frequency components, F(t), of a multiple, n, being an odd multiple of three in accordance with the formula F(t)=a.sub.n cos (n(ωt)) where (n=3, 9, 15, . . . ); the constructively summed harmonic frequency components being provided at the common harmonic frequency output node, the third-harmonic frequency component at the common harmonic frequency output node having the highest amplitude.

Claim 10

The frequency synthesizer of claim 7, wherein the frequency translational element is a multiplier.

Claim 11

The frequency synthesizer of claim 7, further comprising a divider coupled between the output of the third inverter of the ring oscillator and the second input of the detector, and wherein the frequency translation element is a divider.

Claim 12

The frequency synthesizer of claim 7, wherein the loop circuit is a phase locked loop and the detector is a phase detector.

Claim 13

The frequency synthesizer of claim 7, wherein each summing component of the voltage controlled ring oscillator is a passive component selected from at least one of the group consisting of resistors, capacitors and inductors.

Claim 14

The frequency synthesizer of claim 7, wherein the summing components of the voltage controlled ring oscillator are capacitors.

Claim 15

The frequency synthesizer of claim 7, wherein the third-harmonic frequency output from the voltage controlled ring oscillator is electrically coupled to a discrete power transistor to provide a buffered third-harmonic frequency signal.

Claim 16

The frequency synthesizer of claim 7, wherein the voltage controlled ring oscillator and locked loop circuit are provided on an integrated circuit.

Claim 17

The frequency synthesizer of claim 7, wherein the voltage controlled ring oscillator provides a multiplied frequency having a period approaching approximately two inverter propagation delays.

Claim 18

The frequency synthesizer of claim 7, further comprising a low-pass loop filter coupled between the detector and the voltage controlled ring oscillator such that the control voltage is filtered.

Claim 19

A communication device having at least one of a transmitter and a receiver and having a frequency synthesizer including a reference oscillator being coupled to a first divider providing a first divided signal, comprising: a phase locked loop including a phase detector, the first divided signal being coupled to a first input of the phase detector of the phase locked loop, the detector providing a control voltage; and a voltage controlled ring oscillator having harmonic frequency components, the oscillator comprising: a first, second and third inverter each with an input and an output, the output of the first inverter electrically coupled with the input of the second inverter, the output of the second inverter electrically coupled with the input of the third inverter, the output of the third inverter electrically coupled with the input of the first inverter, propagation delays of each inverter controlled by the control voltage; and a first, second and third summing capacitor, the summing capacitors each having one end electrically coupled to an output of the first, second and third inverters, respectively, the other ends of the summing capacitors being commonly electrically connected at a common harmonic frequency output node; the output of the third inverter providing a fundamental output frequency to a second divider which applies a second divided signal to a second input of the phase detector; the summing capacitors passively coupling the harmonic frequency components of ring oscillator such that constructive summation of harmonic frequency components occurs for those frequency components, F(t), of a multiple, n, being an odd multiple of three in accordance with the formula F(t)=a.sub.n cos (n(ωt)) where (n=3, 9, 15 . . . ); the constructively summed harmonic frequency components being provided at the common harmonic frequency output node, the third-harmonic frequency component at the common harmonic frequency output node having the highest amplitude and being provided for the frequency synthesizer.

Claim 20

A communication device having at least one of a transmitter and a receiver and having a frequency synthesizer including a reference oscillator being coupled to a first divider providing a first divided signal, comprising: a phase locked loop including a phase detector, the first divided signal being coupled to a first input of the phase detector of the phase locked loop, the detector providing a control voltage; and a voltage controlled ring oscillator having harmonic frequency components, the oscillator comprising: a first, second and third inverter each with an input and an output, the output of the first inverter electrically coupled with the input of the second inverter, the output of the second inverter electrically coupled with the input of the third inverter, the output of the third inverter electrically coupled with the input of the first inverter, propagation delays of each inverter controlled by the control voltage; and a first, second and third summing capacitor, the summing capacitors each having one end electrically coupled to an output of the first, second and third inverters, respectively, the other ends of the summing capacitors being commonly electrically connected at a common harmonic frequency output node; the output of the third inverter providing a fundamental output frequency to a second divider which applies a second divided signal to a second input of the phase detector; the summing capacitors passively coupling the harmonic frequency components of ring oscillator such that constructive summation of harmonic frequency components occurs for those frequency components, F(t), of a multiple, n, being an odd multiple of three in accordance with the formula F(t)=a.sub.n cos (n(ωt)) where (n=3, 9, 15 . . . ); the constructively summed harmonic frequency components being provided at the common harmonic frequency output node, the third-harmonic frequency component at the common harmonic frequency output node having the highest amplitude and being provided for the frequency synthesizer.

Claim 21

The communication device of claim 17, wherein the third-harmonic frequency output from the frequency synthesizer is capacitively coupled to a discrete power device to provide a buffered third-harmonic frequency signal.

Claim 22

The communication device of claim 17, wherein the voltage controlled ring oscillator and phase locked loop of the frequency synthesizer are provided on a CMOS integrated circuit.