Retriggered oscillator for jitter-free phase locked loop frequency synthesis

Claim 2

A frequency synthesis timebase, comprising: a ring oscillator for generating a first frequency signal and including a plurality of consecutive stages and a plurality of corresponding output taps each tap for providing a phase shift from each succeeding tap; a reference oscillator for generating a second frequency signal; gating means inserted between a pair of said consecutive stages in the ring oscillator for periodically retriggering the ring oscillator in response to said second frequency signal; and phase lock loop (PLL) means for inputting and synchronizing said first frequency signal and said second frequency signal by controlling the resonant frequency of the ring oscillator.

Claim 3

The timebase of claim 1, further comprising: an on-the-fly selector for switching among said plurality of output taps to generate an output frequency according to an order that said output taps are selected.

Claim 4

The timebase of claim 1, wherein: the ring oscillator comprises stages with inverters connected in series; and the gating means comprises a p-gate transistor and an n-gate transistor in series between a power supply controlled by the phase lock loop means and said p-gate is connected to an output of a last inverter stage in said plurality of consecutive stages and said n-gate is connected to an output of the reference oscillator wherein the ring oscillator is retriggered each period of said second frequency signal.

Claim 5

The timebase of claim 1, further comprising: timing path means for delaying an arrival of said second frequency signal to the PLL means wherein the phase of said first frequency signal is offset from said second frequency signal to compensate for a plurality of processing delays acting on said first frequency signal in a transmission to a device-under-test (DUT).

Claim 6

The timebase of claim 1, further comprising: ring symmetry means for adjusting the duty cycle of said first frequency signal to be substantially equal to fifty percent by the insertion of a variable timing path between the ring oscillator and the PLL means.

Claim 7

A frequency synthesis timebase, comprising: a ring oscillator for generating a first frequency signal and including a plurality of consecutive inverter stages and a plurality of corresponding output taps each tap for providing a phase shift from each succeeding tap; a reference oscillator input for accepting a second frequency signal external to the timebase; gating means inserted between a pair of said consecutive stages in the ring oscillator for periodically retriggering the ring oscillator in response to said second frequency signal; phase lock loop (PLL) means for inputting and synchronizing said first frequency signal and said second frequency signal by controlling the resonant frequency of the ring oscillator; an on-the-fly selector for switching among said plurality of output taps to generate a synthesized output frequency according to what order said output taps are selected; timing path means for delaying an arrival of said second frequency sign al to the PLL means wherein the phase of said first frequency signal may be offset from said second frequency signal to compensate for a plurality of processing delays acting on said first frequency signal in a transmission to a device-under-test (DUT); and ring symmetry means for adjusting the duty cycle of said first frequency signal to be substantially equal to 50% by the insertion of a variable timing path between the ring oscillator and the PLL means.

Claim 8

A frequency synthesis timebase, comprising: a ring oscillator for generating a first frequency signal and including a plurality of consecutive inverter stages and a plurality of corresponding output taps each tap for providing a phase shift from each succeeding tap; a reference oscillator input for accepting a second frequency signal external to the timebase; gating means inserted between a pair of said consecutive stages in the ring oscillator for periodically retriggering the ring oscillator in response to said second frequency signal; phase lock loop (PLL) means for inputting and synchronizing said first frequency signal and said second frequency signal by controlling the resonant frequency of the ring oscillator; an on-the-fly selector for switching among said plurality of output taps to generate a synthesized output frequency according to what order said output taps are selected; timing path means for delaying an arrival of said second frequency sign al to the PLL means wherein the phase of said first frequency signal may be offset from said second frequency signal to compensate for a plurality of processing delays acting on said first frequency signal in a transmission to a device-under-test (DUT); and ring symmetry means for adjusting the duty cycle of said first frequency signal to be substantially equal to 50% by the insertion of a variable timing path between the ring oscillator and the PLL means.

Claim 9

A retriggered oscillator timebase, comprising: a phase lock loop controlled first ring for direct retriggering by a reference oscillator outputting a fixed reference frequency and including a plurality of taps at a plurality of successive ring stages; a first on-the-fly selector for adding a ten-bit value to a current-tap selection to enable a next-tap selection wherein such on-the-fly addition can increase the period of a signal each cycle and thereby divide the reference frequency; a pair of second and third retriggered rings for driving a pair of NANO timing edge generators (TEGs) including one for a "present" select and one for a "next" select wherein the pair of rings permits retriggering of one of the rings before the other may complete a whole one-shot cycle; and a second on-the-fly selector for subtracting a value from a present "NANO" select to a next "NANO" select to convert back a timebase to said fixed reference frequency for phase and frequency comparison wherein said subtraction functions as a frequency multiplication with a frequency signal output "t 0fx " that is substantially equal to said fixed reference frequency.

Claim 10

A retriggered oscillator timebase, comprising: a phase lock loop controlled first ring for direct retriggering by a reference oscillator outputting a fixed reference frequency and including a plurality of taps at a plurality of successive ring stages; a first on-the-fly selector for adding a ten-bit value to a current-tap selection to enable a next-tap selection wherein such on-the-fly addition can increase the period of a signal each cycle and thereby divide the reference frequency; a pair of second and third retriggered rings for driving a pair of NANO timing edge generators (TEGs) including one for a "present" select and one for a "next" select wherein the pair of rings permits retriggering of one of the rings before the other may complete a whole one-shot cycle; and a second on-the-fly selector for subtracting a value from a present "NANO" select to a next "NANO" select to convert back a timebase to said fixed reference frequency for phase and frequency comparison wherein said subtraction functions as a frequency multiplication with a frequency signal output "t 0fx " that is substantially equal to said fixed reference frequency.