System comprising field programmable gate array and intelligent memory

Claim 2

A memory integrated circuit comprising: a plurality of memory cells; a clock output signal line; at least one serial output lead; an oscillator for generating a first clock signal and providing said first clock signal on said clock output signal line; and circuitry which obtains a word of data from said memory cells, said word of data comprising a plurality of bits of data, said circuitry also providing said bits of data on said at least one serial output lead in series in synchronization with said first clock signal, wherein said memory cells, clock output signal line, oscillator and circuitry are all formed on a single integrated circuit.

Claim 3

Circuit of claim 1 wherein said memory integrated circuit is part of a logic system comprising a programmable logic device, said memory integrated circuit providing configuration data to said programmable logic device.

Claim 4

Circuit of claim 2 wherein said programmable logic device is a first FPGA, and wherein said memory integrated circuit commences providing said first data to said FPGA upon system power-up.

Claim 5

Circuit of claim 3 wherein said first FPGA comprises means for communicating an output signal indicating when configuration of said first FPGA is complete, and wherein said memory integrated circuit comprises means for receiving said output signal, said memory integrated circuit ceasing providing said data in response to said output signal.

Claim 6

Circuit of claim 4 wherein said first FPGA comprises a FPGA serial output lead, said system further comprising a second FPGA having a data input lead coupled to said FPGA serial output lead and a clock input lead coupled to said clock output signal line, said first FPGA providing configuration data to said second FPGA on said FPGA serial output lead.

Claim 7

Circuit of claim 2 wherein said programmable logic device comprises means for communicating to said memory integrated circuit when said programmable logic device is in a state such that it can receive data from said memory integrated circuit.

Claim 8

Circuit of claim 1 further comprising means for causing said oscillator to commence generating clock signals upon power-up.

Claim 9

Circuit of claim 1 wherein said memory integrated circuit further comprises means for indicating when a last selected bit from said memory cells has been provided on said at least one serial output lead.

Claim 10

Circuit of claim 8 further comprising tri-state buffers for driving said clock output signal line and said at least one serial output lead, and wherein said means for indicating causes said tri-state buffers to go into a tri-state mode when said last selected bit has been provided on said at least one serial output lead.

Claim 11

Memory integrated circuit of claim 1 wherein said memory integrated circuit further comprises means for receiving a second clock signal from a source external to said memory integrated circuit, and wherein said circuitry is operable in a mode wherein said data is provided on said serial output lead in synchronization with said second clock signal.

Claim 12

Memory integrated circuit of claim 10 wherein said clock output signal line is bidirectional so that said memory integrated circuit can both provide clock signals on and receive clock signals from said clock output signal line.

Claim 13

Memory integrated circuit of claim 11 further comprising a multiplexer having a first input lead for receiving a clock signal from said bidirectional clock output signal line and a second input lead for receiving a signal from said oscillator, and wherein the data provided on said at least one serial output lead is in synchronization with the signal on either said first input lead of said multiplexer or said second input lead of said multiplexer.

Claim 14

Memory integrated circuit of claim 11 further comprising a memory cell for controlling whether said memory integrated circuit receives clock signals from said clock output signal line or provides clock signals to said clock output signal line.

Claim 15

Circuit of claim 11 further comprising a mode control input lead for controlling whether said memory integrated circuit receives clock signals from said clock output signal line or provides clock signals to said clock output signal line.

Claim 16

A memory integrated circuit comprising: a data bus; means for storing data and providing words of data on said data bus; an oscillator; a lead for receiving a clock signal from a source external to said memory integrated circuit; and clock means operable in a first mode for generating timing signals in response to said oscillator, said timing signals controlling the timing by which said words of data are provided on said data bus, and for providing control signals so that a device external to said memory integrated circuit can retrieve said data on said data bus, said clock means being operable in a second mode for generating said timing signals in response to said clock signal received from said source external to said memory integrated circuit.

Claim 17

A memory integrated circuit comprising: a data bus; means for storing data and providing words of data on said data bus; an oscillator; a lead for receiving a clock signal from a source external to said memory integrated circuit; and clock means operable in a first mode for generating timing signals in response to said oscillator, said timing signals controlling the timing by which said words of data are provided on said data bus, and for providing control signals so that a device external to said memory integrated circuit can retrieve said data on said data bus, said clock means being operable in a second mode for generating said timing signals in response to said clock signal received from said source external to said memory integrated circuit.

Claim 18

A memory integrated circuit comprising: a plurality of memory cells; a clock output signal line; at least one serial output lead; an oscillator for generating a first clock signal and providing said first clock signal on said clock output signal line; and first circuitry which obtains data from said memory cells, said first circuitry also providing said data on said at least one serial output lead in synchronization with said first clock signal, wherein said memory cells, clock output signal line, oscillator and first circuitry are all formed on a single integrated circuit, wherein said memory integrated circuit further comprises second circuitry which can receive a second clock signal from a source external to said memory integrated circuit, and wherein said first circuitry is operable in a mode wherein said data is provided on said serial output lead in synchronization with said second clock signal.

Claim 19

A memory integrated circuit comprising: a plurality of memory cells; a clock output signal line; at least one serial output lead; an oscillator for generating a first clock signal and providing said first clock signal on said clock output signal line; and first circuitry which obtains data from said memory cells, said first circuitry also providing said data on said at least one serial output lead in synchronization with said first clock signal, wherein said memory cells, clock output signal line, oscillator and first circuitry are all formed on a single integrated circuit, wherein said memory integrated circuit further comprises second circuitry which can receive a second clock signal from a source external to said memory integrated circuit, and wherein said first circuitry is operable in a mode wherein said data is provided on said serial output lead in synchronization with said second clock signal.

Claim 20

Circuit of claim 16 wherein said first circuitry comprises a shift register for receiving said word of data and shifting the bits of said word onto said serial output lead.

Claim 21

Circuit of claim 16 wherein said second circuitry includes a multiplexer for receiving the first and second clock signals, said multiplexer determining whether said memory integrated circuit is responsive to said second clock signal.

Claim 22

Circuit of claim 16 wherein said circuit includes a control lead for receiving a signal from a source external to said memory integrated circuit indicating whether said memory integrated circuit is to be responsive to said second clock signal.

Claim 23

Circuit of claim 16 further comprising a memory cell for providing a signal indicating whether said memory integrated circuit is to be responsive to said second clock signal.

Claim 24

Circuit of claim 16 wherein said clock output signal line is bidirectional, said memory integrated circuit receiving said second clock signal on said clock output signal line.

Claim 25

Circuit of claim 16 further comprising a clock input signal line for receiving said second clock input signal.

Claim 26

Circuit of claim 16 wherein said memory integrated circuit comprises a tristate buffer driving said at least one serial output lead, said tristate buffer going into a tristate mode in response to said means for determining determining that said last bit of configuration data has been communicated to said programmable logic device.

Claim 29

A memory integrated circuit comprising: a plurality with memory cells; a clock output signal line; at least one serial output lead; an oscillator for generating a first clock signal and providing said first clock signal on said clock output signal line; and first circuitry which obtains data from said memory cells, said first circuitry also providing said data on said at least one serial output lead in synchronization with said first clock signal, wherein said memory cells, clock output signal line, oscillator and first circuitry are all formed on a single integrated circuit; second circuitry which can receive a second clock signal from a source external to said memory integrated circuit, wherein said first circuitry is operable in a second mode which provides said data on said at least one serial output lead in synchronization with said second clock signal, and wherein said memory integrated circuit is part of a logic system comprising a programmable logic device, said memory integrated circuit providing configuration data to said programmable logic device, wherein said logic system comprises a plurality of programmable logic devices, said memory integrated circuit providing configuration data to said plurality of programmable logic devices, said system comprising a DONE signal wire, each of said programmable logic devices being coupled to said DONE signal wire and pulling said DONE signal wire to a predetermined voltage level when said programmable logic devices are not done being configured, said DONE signal wire being coupled to said memory integrated circuit, wherein said memory integrated circuit stops sending data on said serial output lead and stops sending clock signals on said clock output signal line when the signal on said DONE signal wire is at a state indicating that all of said programmable logic devices are done being configured.

Claim 30

A memory integrated circuit comprising: a plurality with memory cells; a clock output signal line; at least one serial output lead; an oscillator for generating a first clock signal and providing said first clock signal on said clock output signal line; and first circuitry which obtains data from said memory cells, said first circuitry also providing said data on said at least one serial output lead in synchronization with said first clock signal, wherein said memory cells, clock output signal line, oscillator and first circuitry are all formed on a single integrated circuit; second circuitry which can receive a second clock signal from a source external to said memory integrated circuit, wherein said first circuitry is operable in a second mode which provides said data on said at least one serial output lead in synchronization with said second clock signal, and wherein said memory integrated circuit is part of a logic system comprising a programmable logic device, said memory integrated circuit providing configuration data to said programmable logic device, wherein said logic system comprises a plurality of programmable logic devices, said memory integrated circuit providing configuration data to said plurality of programmable logic devices, said system comprising a DONE signal wire, each of said programmable logic devices being coupled to said DONE signal wire and pulling said DONE signal wire to a predetermined voltage level when said programmable logic devices are not done being configured, said DONE signal wire being coupled to said memory integrated circuit, wherein said memory integrated circuit stops sending data on said serial output lead and stops sending clock signals on said clock output signal line when the signal on said DONE signal wire is at a state indicating that all of said programmable logic devices are done being configured.

Claim 31

Circuit of claim 25 wherein said memory integrated circuit comprises a first tristate buffer driving said clock output signal line and a second tristate buffer driving said serial output lead, said first and second tristate buffers going into a high impedance mode when said DONE signal wire contains a signal indicating that said programmable logic devices are done being configured.

Claim 32

Circuit of claim 26 wherein each of said programmable logic devices comprises an open drain buffer for driving said DONE signal wire.

Claim 33

Circuit of claim 25 wherein each of said programmable logic devices comprise a counter, and each of said programmable logic devices cease pulling said DONE signal wire to said predetermined voltage level when the counters in said programmable logic devices indicate that all of said programmable logic devices are done being configured.

Claim 34

Circuit of claim 25 wherein each of said programmable devices ceases pulling said DONE signal wire to said predetermined voltage level as each programmable logic device is finished being configured.

Claim 35

System comprising: a memory integrated circuit for providing configuration data on a data lead; and a programmable logic device for receiving said configuration data from said data lead and using said configuration data to configure itself, wherein said memory integrated circuit includes means for determining when the last bit of configuration data has been communicated to said programmable logic device, wherein said means for determining comprises means for detecting a code word provided by said memory cells within said memory integrated circuit.

Claim 36

System comprising: a memory integrated circuit for providing configuration data on a data lead; and a programmable logic device for receiving said configuration data from said data lead and using said configuration data to configure itself, wherein said memory integrated circuit includes means for determining when the last bit of configuration data has been communicated to said programmable logic device, wherein said means for determining comprises means for detecting a code word provided by said memory cells within said memory integrated circuit.

Claim 37

system comprising: a data line; a clock line; a first memory device comprising a clock generator for generating a clock signal and providing said clock signal on said clock line, a plurality of memory cells, and circuitry for obtaining data from said memory cells and providing said data on said data line in synchronization with said clock signal, said first memory device also including a last bit line for providing a last bit signal when the last bit of data is provided by said first memory device; and a second memory device comprising a last bit input lead coupled to said last bit line for receiving said last bit signal, a clock generator for generating a clock signal and providing said clock signal on said clock line upon receipt of said last bit signal by said second memory device, a plurality of memory cells, and circuitry which provides data on said data line in synchronization with said clock signal provided by said second memory device clock generator when said last bit signal has been received by said second memory device.

Claim 38

system comprising: a data line; a clock line; a first memory device comprising a clock generator for generating a clock signal and providing said clock signal on said clock line, a plurality of memory cells, and circuitry for obtaining data from said memory cells and providing said data on said data line in synchronization with said clock signal, said first memory device also including a last bit line for providing a last bit signal when the last bit of data is provided by said first memory device; and a second memory device comprising a last bit input lead coupled to said last bit line for receiving said last bit signal, a clock generator for generating a clock signal and providing said clock signal on said clock line upon receipt of said last bit signal by said second memory device, a plurality of memory cells, and circuitry which provides data on said data line in synchronization with said clock signal provided by said second memory device clock generator when said last bit signal has been received by said second memory device.

Claim 39

System of claim 31 wherein said first memory device is a single integrated circuit and said second memory device is a single integrated circuit.

Claim 40

A memory integrated circuit comprising: a clock generator for generating a first clock signal and a second clock signal; an address counter for receiving said first clock signal and providing addresses in response thereto; a memory circuit for receiving said addresses and providing a word of data in response thereto; a shift register for shifting said word of data onto a data output lead in synchronization with said second clock signal; and a clock output lead coupled to said clock generator for providing said second clock signal.

Claim 41

A memory integrated circuit comprising: a clock generator for generating a first clock signal and a second clock signal; an address counter for receiving said first clock signal and providing addresses in response thereto; a memory circuit for receiving said addresses and providing a word of data in response thereto; a shift register for shifting said word of data onto a data output lead in synchronization with said second clock signal; and a clock output lead coupled to said clock generator for providing said second clock signal.