Abstract The system comprises a central information processing unit, an input/output unit, a first-in first-out stack which is connected to receive information from the central information processing unit for sending a "FULL" signal to the central information processing unit when the stack is filled with the information sent from the central information processing unit and for sending thereto an "EMPTY" signal when the stack is empty, an input/output control circuit which operates to transfer the information from the first-in first-out stack to the input/output unit and to detect the state thereof for sending a "READY" signal to the central processing unit when the input/output unit is in a state ready for accepting the information, a command register coupled to the central information processing unit to be set at a particular bit by a bit signal sent from the central processing unit when it receives the "FULL" signal from the first-in first-out stack and the "READY" signal from the input/output control circuit, and a buffer control circuit energized by the output signal from the command register set at the particular bit for applying a transfer commencement command signal to the first-in first-out stack thereby causing it to transfer information to the input/output unit via the input/output control unit.
An information transferring system comprising first and second information processing units, a data buffering first-in first-out stack connected between said first and second information processing units for transferring data therebetween, means for supplying to said first information processing unit from said first-in first-out stack a "FULL" signal when said first-in first-out stack is fully stored with information data, means for supplying to said first information processing unit from said first-in first-out stack an "EMPTY" signal when no information data is stored in said first-in first-out stack, a first control unit connected to said first and second information processing units for supplying to said first information processing unit a "READY" signal indicating that said second information processing unit is in an operable state for accepting information, said first information processing unit including means responsive to said "EMPTY" signal to permit data transfer from said first information processing unit to said first-in first-out stack and means for providing a control signal upon simultaneous receipt of both said "FULL" and "READY" signals, a command register connected to said first information processing unit which is set to a predetermined bit state in response to said control signal from said first information processing unit, and a second control unit connected between said command register and said first-in first-out stack for supplying an output signal to said first-in first-out stack in response to the predetermined bit state of said command register to permit data transfer from said first-in first-out stack to said second information processing unit.
Claim 2
Dependent Claim
250 words
An information transferring system comprising first and second information processing units, a data buffering first-in first-out stack connected between said first and second information processing units for transferring data therebetween, means for supplying to said first information processing unit from said first-in first-out stack a "FULL" signal when said first-in first-out stack is fully stored with information data, means for supplying to said first information processing unit from said first-in first-out stack an "EMPTY" signal when no information data is stored in said first-in first-out stack, a first control unit connected to said first and second information processing units for supplying to said first information processing unit a "READY" signal indicating that said second information processing unit is in an operable state for accepting information, said first information processing unit including means responsive to said "EMPTY" signal to permit data transfer from said first information processing unit to said first-in first-out stack and means for providing a control signal upon simultaneous receipt of both said "FULL" and "READY" signals, a command register connected to said first information processing unit which is set to a predetermined bit state in response to said control signal from said first information processing unit, and a second control unit connected between said command register and said first-in first-out stack for supplying an output signal to said first-in first-out stack in response to the predetermined bit state of said command register to permit data transfer from said first-in first-out stack to said second information processing unit.
Claim 3
Dependent Claim
29 words
An information transferring system according to claim 1 wherein said first information processing unit is a central processing unit and said second information processing unit is an input/output unit.
Claim 4
Dependent Claim
28 words
An information transferring system according to claim 1, wherein said first information processing unit stops data transfer to said first-in first-out stack in response to said "FULL" signal.
Claim 5
Dependent Claim
60 words
An information transferring system according to claim 1, wherein said first control unit is connected between said first-in first-out stack and said second information processing unit and is also connected to said command register to permit data transfer between said first-in first-out stack and said second information processing unit in response to the predetermined bit state of said command register.