Buffer memory system

Claim 1

A memory system comprising: a. an address memory having a plurality of address regions for data messages, said address memory determining the address region for storing a data message and the address region for read out of a data message; b. write means for writing data messages into said regions in sequence; c. selective circuit means in said write means identifying a data message directed to the memory system and generating write request signal for said identified data message, and selectively generating a read request signal; d. read means for reading data messages from said regions in sequence; e. display means in said read means displaying data messages read from said memory at a rate independent of the rate at which data messages are written into said memory; f. first counter means for counting in sequence the number of data messages written into said memory; g. second counter means for counting in sequence the number of data messages read from said memory; h. means for storing information indicating the current status of said data messages; and i. circuit means responsive to said current information in said first and second counter means said circuit means including: 1. a switch means selectively switching the count stored in said first and second counter means to said memory; 2. a control circuit means responsive to said write request signal and generating a first control signal i. to said switch means to transfer the count of said first counter means and to change the count stored in said first counter means, and ii. to said write means to write a data message in said memory, and further responsive to said read request signal and generating a second control signal i. to said switch means to transfer the count of said second counter means to said memory and to change the count stored in said second counter means, and ii. to said read means to read a data message stored in said memory; and 3. third counter means responsive to said first and second control signals and generating a write inhibit signal when data messages are stored in all of said address regions, and further generating a read inhibit signal when all data messages stored in said address regions have been read; 4. said write means responsive to said write inhibit signal thereupon inhibiting writing of said data messages to said memory, and said read means responsive to said read inhibit signal thereupon inhibiting reading of said data messages from said memory.