Apparatus and method of supporting functional design of logic circuit and apparatus and method of verifying functional design of logic circuit

Claim 1

A functional design verification apparatus for verifying the functional design of a logic circuit, comprising: an encode means for accepting an n-bit input signal (n≧2) in which each bit is represented by one of logic signals 0, 1, X, and Z and encoding each bit of said input signal to an encoded bit consisting of a 0-drive bit which indicates whether or not the logic value of said bit can be 0 and a 1-drive bit which indicates whether or not the logic value of said bit can be 1 so as to generate an encoded input signal consisting of a 0-drive word composed of n 0-drive bits and a 1-drive word composed of n 1-drive bits; and a ZX conversion means for accepting said encoded input signal and converting that encoded bit of the n encoded bits in said encoded input signal, which corresponds to the logic signal Z, to the encoded bit which corresponds to the logic signal X so as to generate a converted signal; an output signal evaluation means for accepting said converted signal and obtaining, based on the 0-drive word and 1-drive word of said converted signal, the 0-drive word and 1-drive word which correspond to the result of a logic operation to be subjected to functional simulation so as to generate the encoded output signal consisting of the obtained 0-drive word and 1-drive word; and a decode means for accepting said encoded output signal and restoring a combination of the m-th (1≦m≦n) 0-drive bit in the 0-drive word of said encoded output signal and the mth 1-drive bit in the 1-drive word of the encoded output signal to representation by one of the logic signals 0, 1, X, and Z so as to generate an n-bit output signal.