Logic simulation

Claim 2

A logic simulation method for simulating a circuit including an actual device having an unknown circuit of unknown components and interconnections, comprising the steps of: (a) generating a simulation input signal to be applied to said actual device for which an output of said unknown circuit is to be determined; (b) recovering previously saved contents of internal registers of said actual device, said previously saved contents of said internal registers being contents previously held in said internal registers when said actual device was last operated; (c) storing said recovered previously saved contents in said internal registers of said actual device; (d) operating said actual device using said recovered previously saved contents stored in said internal registers so that said actual device responds to said generated simulation input signals; (e) detecting an output of the actual device as a simulation output of the actual device; (f) saving new contents of said internal registers resulting from operation of said actual device so that the saved new contents are used at a next execution of step (b); and (g) repeating steps (a) to (f).

Claim 3

A logic simulation apparatus for a circuit including a first circuit, comprising: logic simulation means for performing a logic operation of the first circuit based on a simulation circuit model thereof, so as to generate a first simulated output signal of said first circuit to be supplied to an actual device having a second circuit and internal registers; register store means for holding previous contents of said internal registers of said actual device generated when said actual device was last operated; and control means, connected to said logic simulation means and said register store means, for supplying the first simulated output signal to said actual device and for operating said actual device to generate a second simulated output signal in response to said first simultated output; said control means including interrupt means for recovering previous contents of said internal registers held in said register store means, storing said previous contents in said internal registers before supplying said first simulated output signal to said actual device and for storing new contents of said internal registers in said register store means as previous contents of said internal register after operation of said actual device.

Claim 4

A logic simulation apparatus for a circuit including a first circuit, comprising: logic simulation means for performing a logic operation of the first circuit based on a simulation circuit model thereof, so as to generate a first simulated output signal of said first circuit to be supplied to an actual device having a second circuit and internal registers; register store means for holding previous contents of said internal registers of said actual device generated when said actual device was last operated; and control means, connected to said logic simulation means and said register store means, for supplying the first simulated output signal to said actual device and for operating said actual device to generate a second simulated output signal in response to said first simultated output; said control means including interrupt means for recovering previous contents of said internal registers held in said register store means, storing said previous contents in said internal registers before supplying said first simulated output signal to said actual device and for storing new contents of said internal registers in said register store means as previous contents of said internal register after operation of said actual device.

Claim 5

A logic simulation method for a circuit including first and second circuits, comprising the steps of: (a) generating a simulated output signal of the first circuit to be supplied to the second circuit based on a simulation circuit model of the first circuit; (b) recovering previous contents of predetermined internal registers included in an actual device realizing the second circuit, said previous contents being contents held in said internal registers when said actual device was last operated; (c) storing said recovered previous contents of said internal registers in said internal registers; (d) operating said actual device using said previous contents stored in said internal registers so that said actual device responds to the generated simulated output circuit; (e) detecting output of the actual device and using said detected output as an input to the simulation circuit model at a next execution of step (a); and (f) saving new contents of said internal registers resulting from operation of said actual device as previous contents so that the saved new contents are used at a next execution of step (b); and (g) repeating steps (a) to (f).

Claim 6

A logic simulation method for a circuit including first and second circuits, comprising the steps of: (a) generating a simulated output signal of the first circuit to be supplied to the second circuit based on a simulation circuit model of the first circuit; (b) recovering previous contents of predetermined internal registers included in an actual device realizing the second circuit, said previous contents being contents held in said internal registers when said actual device was last operated; (c) storing said recovered previous contents of said internal registers in said internal registers; (d) operating said actual device using said previous contents stored in said internal registers so that said actual device responds to the generated simulated output circuit; (e) detecting output of the actual device and using said detected output as an input to the simulation circuit model at a next execution of step (a); and (f) saving new contents of said internal registers resulting from operation of said actual device as previous contents so that the saved new contents are used at a next execution of step (b); and (g) repeating steps (a) to (f).

Claim 7

A logic simulation method according to claim 3, wherein the step (b) further includes a step of supplying a first interrupt request to said actual device together with said previous contents so that the previous contents are recovered and stored in said internal registers; and wherein step (f) further includes a step of supplying a second interrupt request to said actual device, and saving contents of said internal register supplied at output terminals of said actual device as a result of supply of the second interrupt.