US5731608A — One transistor ferroelectric memory cell and meth…

Claim 1

Independent Claim 179 words

A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a substrate of single crystal silicon, comprising: forming a silicon device area for the FEM gate unit; implanting doping impurities in the silicon device area to form a conductive channel of a first conductivity type for use as a source junction region and a drain junction region; etching an insulating boundary about the device area; forming a gate junction region between the source junction region and drain junction region for the FEM gate unit on the silicon device area; forming a conductive channel precursor layer on the gate junction region; and depositing an FEM gate unit over the gate junction region, including depositing a lower metal layer, a ferroelectric (FE) layer and an upper metal layer, wherein the FEM gate unit is sized on the gate junction region such that any edge of the FEM gate unit is a distance "D" from the edges of the source junction region and the drain junction region, where "D" is between about 50 nm and 300 nm.

Claim 2

Independent Claim 179 words

A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a substrate of single crystal silicon, comprising: forming a silicon device area for the FEM gate unit; implanting doping impurities in the silicon device area to form a conductive channel of a first conductivity type for use as a source junction region and a drain junction region; etching an insulating boundary about the device area; forming a gate junction region between the source junction region and drain junction region for the FEM gate unit on the silicon device area; forming a conductive channel precursor layer on the gate junction region; and depositing an FEM gate unit over the gate junction region, including depositing a lower metal layer, a ferroelectric (FE) layer and an upper metal layer, wherein the FEM gate unit is sized on the gate junction region such that any edge of the FEM gate unit is a distance "D" from the edges of the source junction region and the drain junction region, where "D" is between about 50 nm and 300 nm.

Claim 3

Dependent Claim 63 words

The method of claim 1 wherein forming a conductive channel precursor includes implanting a dopant taken from the group consisting of B and BF 2 at an energy in a range of 3 keV to 10 keV or 15 keV to 50 keV, respectively, and a dose of 1·10 11 cm -2 to 1·10 13 cm -2 to form the conductive channel precursor.

Claim 4

Dependent Claim 39 words

The method of claim 1 which includes annealing the structure at a temperature of about 500° C. to 1100° C. to diffuse ions from the lower metal layer into the gate junction region to form the conductive channel precursor.

Claim 5

Dependent Claim 103 words

The method of claim 1 wherein said depositing the FEM gate unit includes depositing a lower metal layer of Pt, having a thickness of about 20 nm to 100 nm, depositing a FE layer of material taken from the group consisting of Pb(Zr, Ti)O 3 (PZT), SrBi 2 Ta 2 O 9 (SBT), Pb 5 Ge 3 O 11 BaTiO 3 and LiNbO 3 , having a thickness of about 100 nm to 400 nm, and depositing an upper metal layer of material taken from the group consisting of Pt, Ir and Pt/Ir alloy, having a thickness of 20 nm to 100 nm.

Claim 6

Dependent Claim 65 words

The method of claim 1 wherein said implanting doping impurities includes doping the device area with ions taken from the group consisting of As, implanted at an energy of about 40 keV to 70 keV, and phosphorous, implanted at an energy of about 30 keV to 60 keV, the ions having a dose of about 2.10 15 cm -2 to 5·10 15 cm -2 .

Claim 7

Dependent Claim 17 words

The method of claim 1 which includes depositing a layer of TiO over the FEM gate unit.

Claim 8

Independent Claim 264 words

A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a substrate of single crystal silicon comprising: forming a silicon device area for the FEM gate unit; implanting doping impurities in the device area to form a conductive channel of a first conductivity type for use as a source junction region and a drain junction region; etching an insulating boundary about adjacent device areas; forming a gate junction region between the source junction region and drain junction region for the FEM gate unit on the device area; forming a conductive channel precursor on the gate junction region; and depositing an FEM gate unit over the gate junction region, including depositing a lower metal layer of material taken from the group consisting of Pt, Ir and Pt/It alloy, having a thickness of about 20 nm to 100 nm, depositing a ferroelectric (FE) layer of material taken from the group consisting of Pb(Zr, Ti)O 3 (PZT), SrBi 2 Ta 2 O 9 (SBT), Pb 5 Ge 3 O 11 BaTiO 3 and LiNbO 3 , having a thickness of about 100 nm to 400 nm, and depositing an upper metal layer of material taken from the group consisting of Pt, Ir and Pt/Ir alloy, having a thickness of 20 nm to 100 nm, wherein the FEM gate unit is formed on the gate junction region such that any edge of the FEM gate unit is a distance "D" from the edges of the source junction region and the drain junction region, where "D" is between about 50 nm and 300 nm.

Claim 9

Independent Claim 264 words

A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a substrate of single crystal silicon comprising: forming a silicon device area for the FEM gate unit; implanting doping impurities in the device area to form a conductive channel of a first conductivity type for use as a source junction region and a drain junction region; etching an insulating boundary about adjacent device areas; forming a gate junction region between the source junction region and drain junction region for the FEM gate unit on the device area; forming a conductive channel precursor on the gate junction region; and depositing an FEM gate unit over the gate junction region, including depositing a lower metal layer of material taken from the group consisting of Pt, Ir and Pt/It alloy, having a thickness of about 20 nm to 100 nm, depositing a ferroelectric (FE) layer of material taken from the group consisting of Pb(Zr, Ti)O 3 (PZT), SrBi 2 Ta 2 O 9 (SBT), Pb 5 Ge 3 O 11 BaTiO 3 and LiNbO 3 , having a thickness of about 100 nm to 400 nm, and depositing an upper metal layer of material taken from the group consisting of Pt, Ir and Pt/Ir alloy, having a thickness of 20 nm to 100 nm, wherein the FEM gate unit is formed on the gate junction region such that any edge of the FEM gate unit is a distance "D" from the edges of the source junction region and the drain junction region, where "D" is between about 50 nm and 300 nm.

Claim 10

Dependent Claim 63 words

The method of claim 7 wherein forming a conductive channel precursor includes implanting a dopant taken from the group consisting of B and BF 2 at an energy in a range of 3 keV to 10 keV or 15 keV to 50 keV, respectively, and a dose of 1·10 11 cm -2 to 1·10 13 cm -2 to form the conductive channel precursor.

Claim 11

Dependent Claim 45 words

The method of claim 7 which includes annealing the FEM cell at a temperature of about 500° C. to 1100° C. to diffuse ions from the lower metal layer of the FEM gate unit into gate junction region to form the conductive channel precursor layer.

Claim 12

Dependent Claim 25 words

The method of claim 7 which includes forming a channel of the second conductivity type having a thickness of about 50 nm to 100 nm.

Claim 13

Dependent Claim 65 words

The method of claim 7 wherein said implanting doping impurities includes doping the device area with ions taken from the group consisting of As, implanted at an energy of about 40 keV to 70 keV, and phosphorous, implanted at an energy of about 30 keV to 60 keV, the ions having a dose of about 2·10 15 cm -2 to 5·10 15 cm -2 .

Claim 14

Dependent Claim 17 words

The method of claim 7 which includes depositing a layer of TiO over the FEM gate unit.

Claim 15

Dependent Claim 19 words

The method of claim 7 wherein the conductive channel precursor layer underlies the margins of the FEM gate unit.

Claim 16

Dependent Claim 226 words

A ferroelectric memory (FEM) cell comprising: a single-crystal silicon substrate including an active region therein; a source junction region and a drain junction region located in said active region, doped to form a pair of conductive channels of a first conductivity type; a gate junction region located in said active region between said source junction region and said drain junction region, doped to form a conductive channel of a second conductivity type; a conductive channel precursor region located on said gate junction region; a FEM gate unit including a lower metal layer, a ferroelectric (FE) layer and an upper metal layer; wherein said FEM gate unit is sized on the gate junction region such that any edge of said FEM gate unit is a distance "D" from the edges of said source junction region and said drain junction region, where "D" is between about 50 nm and 300 nm; an insulating layer, having an upper surface, overlying said junction regions, said FEM gate unit and said substrate; a source electrode and a drain electrode, each located on the upper surface of said insulating layer and extending therethrough to make electrical contact with their respective junction regions, and a gate electrode located on the upper surface of said insulating layer and extending therethrough to make electrical contact with the upper metal layer of said FEM gate unit.

Claim 17

Dependent Claim 226 words

A ferroelectric memory (FEM) cell comprising: a single-crystal silicon substrate including an active region therein; a source junction region and a drain junction region located in said active region, doped to form a pair of conductive channels of a first conductivity type; a gate junction region located in said active region between said source junction region and said drain junction region, doped to form a conductive channel of a second conductivity type; a conductive channel precursor region located on said gate junction region; a FEM gate unit including a lower metal layer, a ferroelectric (FE) layer and an upper metal layer; wherein said FEM gate unit is sized on the gate junction region such that any edge of said FEM gate unit is a distance "D" from the edges of said source junction region and said drain junction region, where "D" is between about 50 nm and 300 nm; an insulating layer, having an upper surface, overlying said junction regions, said FEM gate unit and said substrate; a source electrode and a drain electrode, each located on the upper surface of said insulating layer and extending therethrough to make electrical contact with their respective junction regions, and a gate electrode located on the upper surface of said insulating layer and extending therethrough to make electrical contact with the upper metal layer of said FEM gate unit.

Claim 18

Dependent Claim 42 words

The FEM cell of claim 14 wherein said conductive channel precursor includes Pt ions therein which diffuse from the lower metal layer of said FEM gate unit during annealing of the structure at a temperature of about 500° C. to 1100° C.

Claim 19

Dependent Claim 65 words

The FEM cell of claim 14 wherein said conductive channel precursor includes ions implanted therein, and wherein the ions are taken from the group consisting of B and BF 2 , implanted at an energy in a range of 3 keV to 10 keV and 15 keV to 50 keV, respectively, and a dose of 1·10 11 cm -2 to 1·10 13 cm -2 .

Claim 20

Dependent Claim 99 words

The FEM cell of claim 14 wherein said FEM gate unit includes a lower metal layer of Pt, having a thickness of about 20 nm to 100 nm, a FE layer of material taken from the group consisting of Pb(Zr, Ti)O 3 (PZT), SrBi 2 Ta 2 O 9 (SBT), Pb 5 Ge 3 O 11 BaTiO 3 and LiNbO 3 , having a thickness of about 100 nm to 400 nm, and an upper metal layer of material taken from the group consisting of Pt, Ir and Pt/Ir alloy, having a thickness of 20 nm to 100 nm.

Claim 21

Dependent Claim 60 words

The FEM cell of claim 14 wherein said active region includes ions taken from the group consisting of As, implanted at an energy of about 40 keV to 70 keV, and phosphorous, implanted at an energy of about 30 keV to 60 keV, the ions having a dose of about 2·10 15 cm -2 to 5·10 15 cm -2 .

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2001-03-23	2001-09-22	2002-03-24	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2005-03-23	2005-09-22	2006-03-24	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2009-03-23	2009-09-22	2010-03-24	$7700.00	Window Closed / Lapsed

One transistor ferroelectric memory cell and method of making the same

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