Method of producing metal semiconductor field effect transistor

Claim 1

A method for fabricating a field effect transistor having a lightly doped drain structure comprising: selectively implanting ions into a semi-insulating GaAs substrate to form a low carrier concentration region; forming a gate electrode on a portion of the low carrier concentration region; implanting ions into the semi-insulating substrate using the gate electrode as a mask, thereby forming first and second intermediate carrier concentration regions at opposite sides of and in contact with the low carrier concentration region and having a higher carrier concentration than the low carrier concentration region; forming insulating sidewall spacers on opposite side surfaces of the gate electrode; implanting ions into the semi-insulating substrate using the gate electrode and the sidewall spacers as a mask, thereby forming first and second high carrier concentration regions at opposite sides of and in contact with the first and second intermediate carrier concentration regions, respectively, the first and second high carrier concentration regions having a higher carrier concentration than the first and second intermediate carrier concentration regions; implanting ions into said first and second intermediate carrier concentration regions at an acceleration energy lower than the acceleration energy used to implant the first and second intermediate carrier concentration regions to a concentration using the gate electrode as a mask, thereby forming first and second regions having a shallower junction depth than the intermediate carrier concentration regions, and having a carrier concentration higher than that of the first and second high carrier concentration regions; and forming spaced apart source and drain electrodes on the first and second regions having a shallower junction depth than the intermediate carrier concentration regions respectively.

Claim 2

A method for fabricating a field effect transistor having a lightly doped drain structure comprising: selectively implanting ions into a semi-insulating GaAs substrate to form a low carrier concentration region; forming a gate electrode on a portion of the low carrier concentration region; implanting ions into the semi-insulating substrate using the gate electrode as a mask, thereby forming first and second intermediate carrier concentration regions at opposite sides of and in contact with the low carrier concentration region and having a higher carrier concentration than the low carrier concentration region; forming insulating sidewall spacers on opposite side surfaces of the gate electrode; implanting ions into the semi-insulating substrate using the gate electrode and the sidewall spacers as a mask, thereby forming first and second high carrier concentration regions at opposite sides of and in contact with the first and second intermediate carrier concentration regions, respectively, the first and second high carrier concentration regions having a higher carrier concentration than the first and second intermediate carrier concentration regions; implanting ions into said first and second intermediate carrier concentration regions at an acceleration energy lower than the acceleration energy used to implant the first and second intermediate carrier concentration regions to a concentration using the gate electrode as a mask, thereby forming first and second regions having a shallower junction depth than the intermediate carrier concentration regions, and having a carrier concentration higher than that of the first and second high carrier concentration regions; and forming spaced apart source and drain electrodes on the first and second regions having a shallower junction depth than the intermediate carrier concentration regions respectively.