US4782031A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making GaAs MOSFET with low source resistance yet having satisfactory leakage current by ion-implantation
Assignee: Panasonic Holdings Corp
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Filing: 1987-03-04
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Granted: 1988-11-01
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Expires: 2007-03-04
Abstract
Abstract In an FET, two first semiconductor regions of higher impurity concentration and smaller thickness, for source electrode and drain electrode, are formed in a second semiconductor region of lower impurity concentration and larger thickness for a gate electrode, thereby obtaining a low source resistance and small leak current.
Inventors
- 👤 Masahiro Hagio
- 👤 Shinichi Katsu
- 👤 Kazuhide Gohda
- 👤 Shutaro Nambu
- 👤 Hiroshi Tsukada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:40
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0614; H10D30/0616; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6738; H10D30/674; H10D30/675; H10D30/80; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/161; H10D64/00; H10D64/60; H10D64/64; H10D62/80; H10D62/85
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
200 words
A method of making a field effect transistor comprising the steps of: forming a gate electrode on a surface of a first semiconductor region located on a semi-insulating surface; forming a thin film on said first semiconductor region, and on top and side surface of said gate electrode; selectively exposing said surface of said first semiconductor region by selectively removing said thin film disposed away from said side surfaces of said gate electrode at a fixed distance; ion-implanting an impurity of one conductivity type through said exposed surface of said first semiconductor region and through the unremoved thin film, thereby forming: (a) a pair of second semiconductor regions of said one conductivity type deeper than said first semiconductor region at a portion beneath said exposed surface of said first semiconductor region; and (b) a pair of third semiconductor regions of said one conductivity type thinner than said first semiconductor region at portions beneath said thin film except for the portion of said first semiconductor surface occupied by said gate electrode and said thin film formed on said side surfaces of said gate electrode; and forming a source electrode and drain electrode on said surface of said second semiconductor regions, respectively.
Claim 2
Independent Claim
200 words
A method of making a field effect transistor comprising the steps of: forming a gate electrode on a surface of a first semiconductor region located on a semi-insulating surface; forming a thin film on said first semiconductor region, and on top and side surface of said gate electrode; selectively exposing said surface of said first semiconductor region by selectively removing said thin film disposed away from said side surfaces of said gate electrode at a fixed distance; ion-implanting an impurity of one conductivity type through said exposed surface of said first semiconductor region and through the unremoved thin film, thereby forming: (a) a pair of second semiconductor regions of said one conductivity type deeper than said first semiconductor region at a portion beneath said exposed surface of said first semiconductor region; and (b) a pair of third semiconductor regions of said one conductivity type thinner than said first semiconductor region at portions beneath said thin film except for the portion of said first semiconductor surface occupied by said gate electrode and said thin film formed on said side surfaces of said gate electrode; and forming a source electrode and drain electrode on said surface of said second semiconductor regions, respectively.
Claim 3
Dependent Claim
15 words
The method of claim 1, wherein said gate electrode is made of TiN or WSi.
Claim 4
Dependent Claim
21 words
The method of claim 1, wherein said thin film consists of Si0 2 or SiN made by using plasma CVD method.
Claim 5
Dependent Claim
24 words
The method of claim 1, wherein impurity concentration of said second and third semiconductor regions is higher than that of said first semiconductor region.
Claim 6
Dependent Claim
16 words
The method of claim 1, wherein said first semiconductor region is formed by epitaxial growth method.
Claim 7
Dependent Claim
15 words
The method of claim 1, wherein said first semiconductor region is formed by ion-implanting method.
Claim 8
Dependent Claim
13 words
The method of claim 1, wherein said semi-insulating substrate is semi-insulating GaAs substrate.
Claim 9
Independent Claim
244 words
A method of making a field effect transistor comprising the steps of: forming a dummy gate on a surface of a first semiconductor region located on a semi-insulating substrate; forming a thin film on said first semiconductor region, and on top and side surfaces of said dummy gate; selectively exposing said surface of said first semiconductor region by selectively removing said thin film disposed away from said side surfaces of said dummy gate at a fixed distannce; ion-implanting impurity of one conductivity type through said exposed surface of said first semiconductor region and through the unremoved thin film, thereby forming: (a) a pair of second semiconductor regions of said one conductivity type deeper than said first semiconductor region at a portion beneath said exposed surface of said first semiconductor region; and (b) a pair of third semiconductor regions of said one conductivity type thinner than said first semiconductor region at portions beneath said thin film except for the portion of said first semiconductor surface occupied by said dummy gate and said thin film formed on said side surfaces of said dummy gate; removing siad thin film; forming a thin layer on said first, second and third removing said dummy gate to expose said surface of said first semiconductor region; forming a gate electrode on said exposed surface of said first semiconductor region; removing said thin layer; and forming a source electrode and a drain electrode on said surface of said second semiconductor regions, respectively.
Claim 10
Independent Claim
244 words
A method of making a field effect transistor comprising the steps of: forming a dummy gate on a surface of a first semiconductor region located on a semi-insulating substrate; forming a thin film on said first semiconductor region, and on top and side surfaces of said dummy gate; selectively exposing said surface of said first semiconductor region by selectively removing said thin film disposed away from said side surfaces of said dummy gate at a fixed distannce; ion-implanting impurity of one conductivity type through said exposed surface of said first semiconductor region and through the unremoved thin film, thereby forming: (a) a pair of second semiconductor regions of said one conductivity type deeper than said first semiconductor region at a portion beneath said exposed surface of said first semiconductor region; and (b) a pair of third semiconductor regions of said one conductivity type thinner than said first semiconductor region at portions beneath said thin film except for the portion of said first semiconductor surface occupied by said dummy gate and said thin film formed on said side surfaces of said dummy gate; removing siad thin film; forming a thin layer on said first, second and third removing said dummy gate to expose said surface of said first semiconductor region; forming a gate electrode on said exposed surface of said first semiconductor region; removing said thin layer; and forming a source electrode and a drain electrode on said surface of said second semiconductor regions, respectively.
Claim 11
Dependent Claim
16 words
The method of claim 8, wherein said dummy gate is made of Si0 2 or SiN.
Claim 12
Dependent Claim
13 words
The method of claim 8, wherein said thin layer is a photoresist layer.
Claim 13
Dependent Claim
17 words
The method of claim 8, wherein said gate electrode consists of TiN, WSi, Al, Ti/Al or Ti/Pt/Au.
Claim 14
Dependent Claim
21 words
The method of claim 8, wherein said thin film consists of Si0 2 or SiN made by using plasma CVD method.
Claim 15
Dependent Claim
24 words
The method of claim 8, wherein impurity concentration of said second and third semiconductor regions is higher than that of said first semiconductor region.
Claim 16
Dependent Claim
16 words
The method of claim 8, wherein said first semiconductor region is formed by epitaxial growth method.
Claim 17
Dependent Claim
16 words
The method of claim 8 , wherein said first semiconductor region is formed by ion-implanting method.
Claim 18
Dependent Claim
13 words
The method of claim 8, wherein said semi-insulating substrate is semi-insulating GaAs substrate.
Claim 19
Independent Claim
235 words
A method of making a GaAs Schottky gate field effect transistor comprising the steps of: forming a Schottky gate electrode on a surface of a first GaAs semiconductor region located on a semi-insulating GaAs substrate; forming a thin film on said first GaAs semiconductor region, and on top and side surfaces of said Schottky gate electrode; selectively exposing said surface of said first GaAs semiconductor region by selectively removing said thin film disposed away from said side surfaces of said Schottky gate electrode at a fixed distance; ion-implanting impurity of one conductivity type through said exposed surface of said first GaAs semiconductor region and through the unremoved thin film, thereby forming: (a) a pair of second GaAs semiconductor regions of said one conductivity type deeper than and having a higher impurity concentration than said first GaAs semiconductor region and at a portion beneath said exposed surface of said first GaAs semiconductor region; (b) a pair of third GaAs semiconductor regions of said one conductivity type thinner than and having a higher impurity concentration than said first GaAs semiconductor region and at portions beneath said thin film except for the portion of said first GaAs semiconductor surface occupied by said Schottky gate electrode and said thin film formed on said side surfaces of said Schottky gate electrode; and forming a source electrode and a drain electrode on said surface of sad second GaAs semiconductor regions, respectively.
Claim 20
Independent Claim
235 words
A method of making a GaAs Schottky gate field effect transistor comprising the steps of: forming a Schottky gate electrode on a surface of a first GaAs semiconductor region located on a semi-insulating GaAs substrate; forming a thin film on said first GaAs semiconductor region, and on top and side surfaces of said Schottky gate electrode; selectively exposing said surface of said first GaAs semiconductor region by selectively removing said thin film disposed away from said side surfaces of said Schottky gate electrode at a fixed distance; ion-implanting impurity of one conductivity type through said exposed surface of said first GaAs semiconductor region and through the unremoved thin film, thereby forming: (a) a pair of second GaAs semiconductor regions of said one conductivity type deeper than and having a higher impurity concentration than said first GaAs semiconductor region and at a portion beneath said exposed surface of said first GaAs semiconductor region; (b) a pair of third GaAs semiconductor regions of said one conductivity type thinner than and having a higher impurity concentration than said first GaAs semiconductor region and at portions beneath said thin film except for the portion of said first GaAs semiconductor surface occupied by said Schottky gate electrode and said thin film formed on said side surfaces of said Schottky gate electrode; and forming a source electrode and a drain electrode on said surface of sad second GaAs semiconductor regions, respectively.
References Cited (Backward Citations)
US4119995A
Cited
US4119995B1
Cited
US4112455A
Cited
JPS5414075A
Cited
US4304042A
Cited
US4277882A
Cited
US4377030A
Cited
US4422087A
Cited
US4559238A
Cited
US4503599A
Cited
US4540446A
Cited
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